Main Group

main / RISC-V main group
************************* RISC-V Main Members Group ************************* Welcome to the RISC-V Members group server! The RISC-V Foundation is an open-source non-profit foundation managing the IP and development activities for the RISC-V Instruction Set Architecture (ISA), an open source hardware initiative that is rapidly transforming the way microprocessors are made. The subgroups here are moderated, members-only discussions related to the development of the RISC-V ISA. The primary website for the RISC-V architecture is at https://riscv.org. To become a member of the RISC-V Foundation community, please see https://riscv.org/membership-application The groups on this server are currently restricted to members who have signed the membership agreement. There is also a set of public mailing lists that does not require membership - you can join these discussions here: https://groups.google.com/a/groups.riscv.org This server provides discussion lists, calendars, and other services for RISC-V members, including: * technical working groups (tech-*) * marketing working groups (mktg-*) * special interest discussion groups (sig-*) * administrative groups This group " *main* " maintains profiles for the members of all lists underneath it. You will not receive email from this group, and you must belong to it in order to subscribe to the discussions in subgroups underneath it. DO NOT unsubscribe from this list unless you want to remove yourself from all RISC-V member groups. Instead, manage your subscriptions to each subgroup individually. You can view and join these subgroups by clicking "Subgroups" on the left side of this screen. In addition, please make sure to join the subgroup " *allmem* ". Within each group, after joining the group, you can view *Messages* , *Calendar* , *Files* , and *Wiki* using the links on the left side. You can return to the main group by clicking " *Your groups* " at the top and choosing " *RISC-V main group* ", and you can view server-wide information by clicking the *RISCV* text at the very top left of the screen. You can subscribe to each group's calendar individually, but most people find it easier to subscribe to all of your subgroup calendars at once. Click *RISCV* and then *Your Calendar* to view or subscribe to a compilation of all of the calendars for the subgroups to which you are subscribed. To subscribe, scroll to the bottom of a calendar page, click " *Subscribe to Calendar* ", make a copy of the iCalendar URL and subscribe (not import) using your calendar software. Note that some users of Outlook have described time zone issues with iCalendar links, so please double-check meeting times. Finally, for every group, you can choose whether your profile is visible to others. By default, your profile is not visible. To make it visible, click your name in the upper right corner and choose " *My Account* ", then click the *Identity* tab. You can customize your profile for each group you are subscribed to. Changes made to your account profile will automatically apply to each group profile, with the exception of those specific fields in each group profile that you've previously customized.
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1036 Members, 0 Topics, Archives are visible to subscribers only, Restricted

Subgroups You Can Join

Technical Committee

RISC-V Technical Committee

  • tech / RISC-V Technical Committee
    Welcome to the RISC-V Technical Committee secure area. In this section of the RISC-V Foundation workspace you will find meeting minutes, showings, reports, schedules, and project descriptions compiled by the Technical Committee, updated on a regular basis. Some areas are under construction, awaiting further developments, but all areas are included to indicate the future direction of the site. Access to this area is restricted to members of the Technical Committee (primary/alternate/observer) and the Board of Directors. Please keep watching this space for new information and developments.
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    638 Members, 130 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-base-isa / Base ISA Ratification
    Base ISA Ratification
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    54 Members, 27 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-bitmanip / BitManip Task Group
    The BitManip work group will define extensions to the Unprivileged ISA that are comprised of bit-based instructions. These extensions are intended to enable the development of code that is substantially more performant and efficient that what is possible with the base instructions. Performance testing will be conducted by compiling or hand-assembling routines and then measuring performance improvement in a RISC-V modelling environment. Where possible, all or portions of standard benchmark tests will be employed in this testing. The new instructions will include operations from one or more of the following categories: bit counts, shift/rotate, insert/extract, set/clear, permute, and logical/mask. A base extension will include commonly used functions that are simpler to implement. An extended extension will be proposed should there be instructions that provide even more performance and power savings at a cost of more complexity.
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    77 Members, 143 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-chairs / Technical Committee Task Group Chairs and Vice Chairs
    Technical Committee Task Group Chairs and Vice Chairs
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    31 Members, 72 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-compliance / Compliance Task Group
    Compliance Task Group
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    89 Members, 258 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-crypto-ext / Cryptographic Extensions Task Group
    The Cryptographic Extensions Task Group will propose ISA extensions to the vector extensions for the standardized and secure execution of popular cryptography algorithms.  To ensure that processor implementers are able to support a wide range of performance and security levels the committee will create a base and an extended specification. The base will be comprised of low-cost instructions that are useful for the acceleration of common algorithms. The extended specification will include greater functionality, reserve encodings for more algorithms, and will facilitate improved security of execution and higher performance.   The scope will include symmetric and asymmetric cryptographic algorithms and related primitives such as message digests.  The committee will also make ISA proposals regarding the use of random bits and secure key management.
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    88 Members, 89 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-debug / Debug Task Group
    Welcome to the RISC-V Debug Task Group secure area. The Debug Task Group's goal is the ratification of a specification for how to enable low-level hardware debugging on RISC-V implementations.  In this section of the RISC-V Foundation Workspace you will find meeting minutes and slides, updated on a regular basis. Access to this area is restricted to members of the Debug Task Group.  For updates, keep an eye on this space and the task group mailing list:debug@workspace.riscv.org. Success Criteria: A Foundation-Ratified Specification for Run/Halt debug of RISC-V based systems. This is desired by the 8th RISC-V Workshop in Barcelona, May 2018. Auxiliary Goals:  Reference implementations & reference SW implementations, Documented SW conventions for debug-related tasks; Explicitly Out of Scope: Trace specification
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    114 Members, 283 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-fast-int / Fast Interrupts Task Group
    Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
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    74 Members, 35 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-formalspec / Formal Specification Task Group
    This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness. It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers.  It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs. [ This work is closely related to and complementary to the work of the  Memory Model Task Group ]
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    92 Members, 188 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-j-ext / J Extension Task Group
    The RISC-V J extension aims to make RISC-V an attractive target for languages that are traditionally interpreted or JIT compiled, or which require large runtime libraries or language-level virtual machines. Examples include (but are not limited to) C#, Go, Haskell, Java, JavaScript, OCaml, PHP, Python, R, Ruby, Scala or WebAssembly. Among other topics, the group expects to collaborate with several existing RISC-V extension working groups.
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    40 Members, 68 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-memory-model / Memory Model Task Group
    The memory model task group charter is to define the memory consistency model for the RISC-V architecture, to produce relevant documentation and supplementary material (such as formal mathematical specifications and compliance test cases), and to work with the other task groups to ensure their own specifications remain compatible with the memory model.
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    123 Members, 285 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-opcodes / OpCode Space Management Task Group
    The OpCode Space Management Task Group is a standing group with the task of allocating reserved opcode space for new proposed standard extensions.  The group works with task groups developing new standard extensions to avoid conflicts with other current and planned future extensions.
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    24 Members, 1 Topic, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-p-ext / P Extension Task Group
    Define and ratify Packed-SIMD DSP extension instructions operating on XLEN-bit integer registers for embedded RISC-V processors. The TG will also define compiler intrinsic functions that can be directly used in high-level programming languages.
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    60 Members, 9 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-privileged / Privileged Specification Task Group
    The Privileged Architecture Task Group's charter is to define and facilitate the ratification of a Privileged Architecture Specification suitable for embedded systems and Unix-like operating systems.
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    132 Members, 113 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-sv128 / SV128 Task Group
    CHARTER FOR DEFINITION OF SV128 FOR RISC-V ARCHITECTURE Using minicomputers as a starting point, logical addresses from the early to late 70’s grew from 16 to 32 bits. The main driver was main memory dram technology increases. In the early 90’s, the logical address space increased to 64 bits. Again, the main driver was the main memory dram technology increases. Today, in addition to increases in main memory technologies, the creation of cluster and node multicomputer systems has resulted in a step function in memory capacities. This coupled with newer contemporary memory reference models such as PGAS and WEB based referencing models, as well as the introduction of non-volatile memory, results is the need to define SEMANTICS for data references. This contrasts with previous logical address expansion that extended the address space (flat addressing). Consequently SV128, should be capable of BOTH globally, directly referencing memory, independent of the underlying system architecture, as well as incorporating contemporary security models. Additionally, compatibility with existing RV32 and RV64 executable images need to be supported. As part of this effort, where ever possible, formal methods should be utilized. The SV128 working group, will define a 128 virtual address space in 6 months.
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    30 Members, 21 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-tee / Trusted Execution Environment Task Group
    The mission of RISC-V trusted execution environment working group are: To define an architecture specification to support trusted execution environment for  RISC-V processors To provide necessary implementation guidelines and/or recommendations to assist hardware developers to realize the specification To enable the development of necessary components, such as compiler, simulation model, hardware, and software components to support the specification
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    155 Members, 214 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-toolchain / Software Task Group
    Welcome to the Software Task Group. The goal of this task group is to coordinate efforts to build the RISC-V software ecosystem and to standardize RISC-V software interfaces.
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    105 Members, 53 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-trace / Processor Trace Task Group
    The group shall standardize both a hardware interface to the RISCV core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors. The interfaces are to provide enough information for: Instruction Trace.  The interfaces should be suitable for in-order and out-of-order cores with extensions.  The group will standardize the data format for: Compressed branch trace so that program flow can be reconstructed by debugging tools.   The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.
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    66 Members, 146 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-unixplatformspec / UNIX-Class Platform Specification Task Group
    UNIX-Class Platform Specification Task Group
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    43 Members, 25 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • tech-vector-ext / Vector Extension Task Group
    The V Extension Task Group is tasked with developing the specification for the RISC-V base V vector extension, including written documentation, executable model, and compliance suite.  The group is also responsible for outlining how future vector extensions can build on this baseline.
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    160 Members, 222 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Program Commitee

RISC-V Workshops Program Committee

  • prog / RISC-V Program Committee for Workshops
    The Program Committee for Workshops is responsible for guiding the content and supporting/advising on the organization of  RISC-V Workshops.
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    25 Members, 56 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • prog-chennai / RISC-V Program Committee for Workshops in Chennai
    RISC-V Program Committee for Workshops in Chennai
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    8 Members, 0 Topics, Archives Viewable Only By Members, Restricted
  • prog-shanghai / RISC-V Program Committee for Workshops in Shanghai
    RISC-V Program Committee for Workshops in Shanghai
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    7 Members, 1 Topic, Archives Viewable Only By Members, Restricted, Last Post:
  • prog-summit / RISC-V Program Committee for RISC-V Summit
    RISC-V Program Committee for RISC-V Summit
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    9 Members, 14 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Marketing Committee

RISC-V Marketing Committee

  • mktg / RISC-V Marketing Committee
    Welcome to the RISC-V Marketing Committee. In this section you will find a calendar for upcoming meetings along with  documentation relating to our efforts to drive awareness and outbound messaging on RISC-V. Chair: Ted Marena Vice-Chair: Michael Gielda
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    230 Members, 509 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-apac / RISC-V Marketing Asia Pacific Regional Task Group
    Promote awareness, learning and adoption of the RISC-V ISA in the Asia Pacific Region.
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    53 Members, 87 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-chairs / RISC-V Marketing Committee Task Group Chairs & Vice Chairs
    RISC-V Marketing Committee Task Group Chairs & Vice Chairs
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    10 Members, 4 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-content / RISC-V Marketing Content Task Group
    The aim of Marketing Content Task Group is to drive the content creation and curation efforts for RISC-V marketing, making sure that relevant information is available, well presented, clear and comprehensive. The Content TG recommends activities related to e.g. the RISC-V website, newsletters, training material, and the Foundation's internal communication.
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    32 Members, 140 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-events / RISC-V Marketing Events Task Group
    RISC-V Marketing Events Task Group
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    64 Members, 97 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-ew2019 / RISC-V Marketing Committee - EW 2019 Task Group
    RISC-V Marketing Committee - EW 2019 Task Group Chair: Jo Windel Vice-Chair: Kevin McDermott
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    17 Members, 156 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-outreach / Open Source and University Outreach Task Group
    Welcome to the Open Source and University Outreach Task Group. The goal of this task group is to coordinate outreach to the open source community as well as researchers and educators in academia.
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    43 Members, 52 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • mktg-research / RISC-V Marketing Research Task Group
    DRAFT Charter 1. Identify targeted market research on RISC-V which would be of interest to the RISC-V membership at large. 2. Facilitate and support research by 3rd party analyst firms on selected topics. 3. In conjunction with Racepoint and Foundation staff, liaise with market researchers and analysts who are preparing RISC-V related reports. (Note: At this time, it is anticipated that the targeted research will not be funded or sponsored by the foundation or by member sponsorships. Rather, the resulting reports will be offered for a fee by the research organizations).
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    12 Members, 16 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Board of Directors

Board-level discussions

  • bod / RISC-V Board of Directors
    RISC-V Board of Directors
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    11 Members, 479 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • bod-exec-council / RISC-V Board of Directors Executive Council
    RISC-V Board of Directors Executive Council
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    7 Members, 0 Topics, Archives Viewable Only By Members, Restricted
  • chinaadvcomm / China Advisory Committee
    Building on the RISC-V Foundation’s growing footprint in China across more than 25 organizations and universities, the China Advisory Committee will guide the RISC-V Foundation’s education and adoption strategies to further accelerate the RISC-V ecosystem in the region. Participation in this committee is open to foundation members who have significant China-based operations.
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    7 Members, 1 Topic, Archives Viewable Only By Members, Restricted, Last Post:
  • eligible-voters / RISC-V Eligible Voters
    This list contains primary voters from all eligible member companies: Platinum, Gold, and Silver. This list is used for BOD candidate elections and spec approval.
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    130 Members, 4 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Special Interest Groups

  • sig / Special Interest Groups
    Special Interest Groups (SIGs) are places for discussions about specific topics of interest to the RISC-V community. This top-level group is the home for meta-discussions about SIGs in general. See the other sig- subgroups for particular topics.
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    1 Member, 0 Topics, Archives Viewable By Parent Group
  • sig-hpc / Special Interest Group: High-Performance Computing (HPC)
    Special Interest Group: High-Performance Computing (HPC) This group is for discussions around HPC related to RISC-V
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    5 Members, 0 Topics, Archives Viewable By Parent Group
  • sig-japan / Special Interest Group: Japan
    Japan Special Interest Group
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    2 Members, 0 Topics, Archives Viewable By Parent Group
  • allmem / All Members
    ************************ RISC-V All-Members Group ************************ Welcome to the RISC-V Members group server! The subgroups here are moderated, members-only discussions related to the development of the RISC-V ISA. The primary website for the RISC-V architecture is at https://riscv.org. To become a member of the RISC-V Foundation community, please see https://riscv.org/membership-application The groups on this server are currently restricted to members who have signed the membership agreement. There is also a set of public mailing lists that does not require membership - you can join these discussions here: https://groups.google.com/a/groups.riscv.org This server provides discussion lists, calendars, and other services for RISC-V members, including: * technical working groups (tech-*) * marketing working groups (mktg-*) * special interest discussion groups (sig-*) * administrative groups This group " allmem " is for announcements to all members. Traffic on this list is extremely low. Discussions take place in other groups - you can view and join these subgroups by clicking "Subgroups" on the left side of this screen. Within each group, after joining the group, you can view Messages , Calendar , Files , and Wiki using the links on the left side. You can return to the main group by clicking " Your groups " at the top and choosing " RISC-V main group ", and you can view server-wide information by clicking the RISCV text at the very top left of the screen. You can subscribe to each group's calendar individually, but most people find it easier to subscribe to all of your subgroup calendars at once. Click RISCV and then Your Calendar to view or subscribe to a compilation of all of the calendars for the subgroups to which you are subscribed. To subscribe, scroll to the bottom of a calendar page, click " Subscribe to Calendar ", make a copy of the iCalendar URL and subscribe (not import) using your calendar software. Note that some users of Outlook have described time zone issues with iCalendar links, so please double-check meeting times. Finally, for every group, you can choose whether your profile is visible to others. By default, your profile is not visible. To make it visible, click your name in the upper right corner and choose " My Account ", then click the Identity tab. You can customize your profile for each group you are subscribed to. Changes made to your account profile will automatically apply to each group profile, with the exception of those specific fields in each group profile that you've previously customized.
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    750 Members, 74 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • security / RISC-V Security Standing Committee
    RISC-V Security Standing Committee Main Goals: ● Promote RISC-V as an ideal vehicle for the security community ● Liaise with other internal RISC V committees and with external security committees ● Create an information repository on new attack trends, threats and countermeasures ● Identify top 10 open challenges in security for the RISC-V community to address ● Propose security committees (Marketing or Technical) to tackle specific security topics ● Recruit security talent to the RISC-V ecosystem (e.g., into committees) ● Develop consensus around best security practices for IoT devices and embedded systems
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    111 Members, 273 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • test-group
    Don't join this
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    1 Member, 10 Topics, Archives Viewable Only By Members, Restricted, Last Post: