Main Group

RISC-V main group
************************* RISC-V Main Members Group ************************* Welcome to the RISC-V Members group server. RISC-V International is an open-source non-profit organization managing the IP and development activities for the RISC-V Instruction Set Architecture (ISA), an open source hardware initiative that is rapidly transforming the way microprocessors are made. The subgroups here are moderated, members-only discussions related to the development of the RISC-V ISA. The primary website for the RISC-V architecture is at https://riscv.org. To become a member of the RISC-V International community, please see https://riscv.org/membership-application *PLEASE NOTE: Participation in the groups on this server is currently restricted to members who have signed the membership agreement. If your organization has is already a member, you do not need to sign a new membership agreement. Send email to info@riscv.org and request to be added to this server. If your organization would like to join RISC-V, or if you would like to participate as an individual person with an Individual membership, you can fill out the membership agreement ( https://riscv.org/membership ). * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- All technical groups operate with public visibility. We welcome everyone to view the mail archives. If you wish to subscribe to a list and participate in the discussion, please visit the membership application link above. There is also a set of public discussion lists that does not require membership. You can join these discussions here: https://groups.google.com/a/groups.riscv.org This server provides discussion lists, calendars, and other services for RISC-V members. More details are at https://riscv.org/getting-started-in-risc-v/
Created:
1872 Members, 0 Topics, Archive is visible to members only, Restricted

Subgroups You Can Join

Technical Task Groups & Committees

RISC-V Technical Task Groups & Committees

  • RISC-V Security Standing Committee
    RISC-V Security Standing Committee Main Goals: ● Promote RISC-V as an ideal vehicle for the security community ● Liaise with other internal RISC V committees and with external security committees ● Create an information repository on new attack trends, threats and countermeasures ● Identify top 10 open challenges in security for the RISC-V community to address ● Propose security committees (Marketing or Technical) to tackle specific security topics ● Recruit security talent to the RISC-V ecosystem (e.g., into committees) ● Develop consensus around best security practices for IoT devices and embedded systems
    Created:
    193 Members, 28 Topics, Public Archives, Last Post:
  • Tech: Software Standing Committee
    Software Standing Committee Welcome to the Software Task Group. The goal of this task group is to coordinate efforts to build the RISC-V software ecosystem and to standardize RISC-V software interfaces.
    Created:
    174 Members, 26 Topics, Public Archives, Last Post:
  • Tech: General Technical Discussions and Announcements
    Welcome to the RISC-V Technical discussion list. In this section of the RISC-V Foundation workspace you will find meeting minutes, showings, reports, schedules, and project descriptions compiled by the Technical Committee, updated on a regular basis. Some areas are under construction, awaiting further developments, but all areas are included to indicate the future direction of the site. Access to this area is restricted to members of the Technical Committee (primary/alternate/observer) and the Board of Directors. Please keep watching this space for new information and developments.
    Created:
    702 Members, 73 Topics, Public Archives, Last Post:
  • Tech: Base ISA Ratification Task Group
    *********************** *Base ISA Ratification* *********************** *Charter* : To define, specify, and ratify the unprivileged RISC-V base architectures and standard extensions.
    Created:
    92 Members, 0 Topics, Public Archives
  • Tech: BitManip Task Group
    ******************* BitManip Task Group ******************* The BitManip work group will define extensions to the Unprivileged ISA that are comprised of bit-based instructions. These extensions are intended to enable the development of code that is substantially more performant and efficient that what is possible with the base instructions. Performance testing will be conducted by compiling or hand-assembling routines and then measuring performance improvement in a RISC-V modelling environment. Where possible, all or portions of standard benchmark tests will be employed in this testing. The new instructions will include operations from one or more of the following categories: bit counts, shift/rotate, insert/extract, set/clear, permute, and logical/mask. A base extension will include commonly used functions that are simpler to implement. An extended extension will be proposed should there be instructions that provide even more performance and power savings at a cost of more complexity.
    Created:
    149 Members, 26 Topics, Public Archives, Last Post:
  • Tech: Task Group Chairs and Vice Chairs
    Technical Committee Task Group Chairs and Vice Chairs
    Created:
    50 Members, 208 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • Tech: Cache Management Operations Task Group (CMO)
    Cache Management Operations Task Group
    Created:
    51 Members, 13 Topics, Public Archives, Last Post:
  • Tech: Code Size Reduction Task Group
    *Code Size Reduction Task Group* *Chair* : Tariq Kurd tariq.kurd@huawei.com ( tariq.kurd@huawei.com ) *Vice-chair* Nidal Faour Nidal.Faour@wdc.com ( Nidal.Faour@wdc.com ) *Charter* The code size reduction TG will develop a holistic solution to reducing code size, covering different profiles to be competitive with other core implementations of other architectures of a similar class. Priority is given to small embedded cores which often have very constrained memory sizes and so code size reduction is most important for cost reduction. Larger/higher performance cores will also benefit from reduced code size. *Output* The output will be improved toolchain technology to reduce code size, and also at least one ISA extension to reduce code size with toolchain support in both GCC and LLVM. If any part of any future ISA extension risks complicating the design of high performance cores, then those instructions will be in a different subset so that they can be excluded. Therefore high performance cores will also benefit from improved toolchain technology and also an ISA extension. The TG may decide to develop an alternative to the C-extension and acknowledge that incompatibility caused by this would be undesirable. Therefore the benefit would have to be very high. Output from the TG could include coding recommendations to improve code size. *Initial Roadmap* - Build a benchmark / application suite for measuring code size - Collect existing proposals for code size reduction ISA extensions - I mprove compiler support in known weak areas, such as function call prologue/epilogue - Add a new code size reduction ISA extension using currently reserved encodings, to address cases where the toolchain improvements alone cannot solve the code size problem *Other TGs* This TG will handle all aspects of making RISC-V code-size competitive.  Zfinx, EABI and the J-extension all already have related work, but other tasks groups may as well so this is not a complete list. New TGs may be spawned as required to complete the objective. The TG will report to the software standing committee, and will work with the unprivileged standing committee to ratify any ISA extensions.
    Created:
    60 Members, 16 Topics, Public Archives, Last Post:
  • Tech: Compliance Task Group
    ********************* Compliance Task Group ********************* Define coverage requirements for RV32I compliance tests, release compliance test format spec, release compliance suite for RV32I
    Created:
    117 Members, 93 Topics, Public Archives, Last Post:
  • Tech: Configuration Structure Task Group
    Configuration Structure Task Group github: https://github.com/riscv/configuration-structure
    Created:
    53 Members, 70 Topics, Public Archives, Last Post:
  • Tech: Cryptographic Extensions Task Group
    *********************************** Cryptographic Extensions Task Group *********************************** The Cryptographic Extensions Task Group will propose ISA extensions to the vector extensions for the standardized and secure execution of popular cryptography algorithms.  To ensure that processor implementers are able to support a wide range of performance and security levels the committee will create a base and an extended specification. The base will be comprised of low-cost instructions that are useful for the acceleration of common algorithms. The extended specification will include greater functionality, reserve encodings for more algorithms, and will facilitate improved security of execution and higher performance.   The scope will include symmetric and asymmetric cryptographic algorithms and related primitives such as message digests.  The committee will also make ISA proposals regarding the use of random bits and secure key management.
    Created:
    183 Members, 126 Topics, Public Archives, Last Post:
  • Tech: Debug Task Group
    **************** Debug Task Group **************** Welcome to the RISC-V Debug Task Group. The Debug Task Group's goal is the ratification of a specification for how to enable low-level hardware debugging on RISC-V implementations.  In this section of the RISC-V Foundation Workspace you will find meeting minutes and slides, updated on a regular basis. Access to this area is restricted to members of the Debug Task Group.  For updates, keep an eye on this space and the task group mailing list:debug@workspace.riscv.org. Success Criteria: A Foundation-Ratified Specification for Run/Halt debug of RISC-V based systems. This is desired by the 8th RISC-V Workshop in Barcelona, May 2018. Auxiliary Goals:  Reference implementations & reference SW implementations, Documented SW conventions for debug-related tasks; Explicitly Out of Scope: Trace specification
    Created:
    179 Members, 63 Topics, Public Archives, Last Post:
  • Tech: EABI Task Group
    Task group working on EABI development
    Created:
    40 Members, 8 Topics, Public Archives, Last Post:
  • Tech: Fast Interrupts Task Group
    ************************* Fast Interrupt Task Group ************************* Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.
    Created:
    118 Members, 43 Topics, Public Archives, Last Post:
  • Tech: Formal Specification Task Group
    ******************************* Formal Specification Task Group ******************************* This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness. It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers.  It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs. [ This work is closely related to and complementary to the work of the  Memory Model Task Group ]
    Created:
    126 Members, 2 Topics, Public Archives, Last Post:
  • Tech: J Extension Task Group
    ********************** J Extension Task Group ********************** The RISC-V J extension aims to make RISC-V an attractive target for languages that are traditionally interpreted or JIT compiled, or which require large runtime libraries or language-level virtual machines. Examples include (but are not limited to) C#, Go, Haskell, Java, JavaScript, OCaml, PHP, Python, R, Ruby, Scala or WebAssembly. Among other topics, the group expects to collaborate with several existing RISC-V extension working groups.
    Created:
    90 Members, 28 Topics, Public Archives, Last Post:
  • Tech: Memory Model Task Group
    *********************** Memory Model Task Group *********************** The memory model task group charter is to define the memory consistency model for the RISC-V architecture, to produce relevant documentation and supplementary material (such as formal mathematical specifications and compliance test cases), and to work with the other task groups to ensure their own specifications remain compatible with the memory model.
    Created:
    165 Members, 0 Topics, Public Archives
  • Tech: Nexus Trace Task Group
    ********************** Nexus Trace Task Group ********************** The Nexus Trace Task Group is responsible for analysis of Nexus IEEE-ISTO 5001™ standard and it's applicability for trace of RISC-V cores. The Nexus standard is well established, silicon proven and extensively documented. It's necessary to define parts of the standard that are applicable to RISC-V trace. Github repo: *https://github.com/riscv/tg- nexus-trace ( https://github.com/riscv/tg-nexus-trace )* contains working documents and reference C code for encoder and decoder. * * The following parts of Nexus specification will be addressed: * Nexus compatible trace encoding * Trace control * Trace configuration * On-chip and off-chip trace routing * Physical trace connector options This group will not address the debug part of the Nexus standard. The group’s progress shall be evaluated after 4 months, at which time the charter may be revised if necessary to narrow the scope of effort. Chair: Robert Chyla Robert.Chyla@iar.com Vice-Chair: Neal Stollon Neal.Stollon@wdc.com
    Created:
    69 Members, 40 Topics, Public Archives, Last Post:
  • Tech: Software Overlay Task Group
    *************************** Software Overlay Task Group *************************** github: TBD *Motivation* In the early days of embedded computing there was a technique to load code in Real-Time at the moment it was needed for execution. Back than memory was expensive in all aspects. Similarly, today, IoT devices are very restricted with memory size and power. Due to those requirements, the need arises a need to revive the overlay concept to fit to RISC-V ISA, and use the RISC-V toolchain to support it. Charter The Software Overlay TG will specify the requirements for the software overlay feature, both from the FW manager  engine and from toolchain aspects, all which will be based on the current RISC-V ISA and extensions. *Deliverable* Full operation software stack to be part of RISC-V toolchain, includes runtime software and toolchain support . Initial Roadmap (by Phases) Gather * Gathering specification and requirements: what we wish this feature to contain * Making a generic software requirement to be approved by the TG Design * Establish a software spec based on the requirements * Designing RT FW, using RISC-V ISA * Designing Toolchain usage * Write HLD (High level design) for the RT engine Implementation * Implementation and LLD (low level design) * Deployment * Write Test suite
    Created:
    12 Members, 0 Topics, Public Archives
  • Tech: P Extension Task Group
    ********************** P Extension Task Group ********************** *Charter* : Define and ratify Packed-SIMD DSP extension instructions operating on XLEN-bit integer registers for embedded RISC-V processors. The TG will also define compiler intrinsic functions that can be directly used in high-level programming languages.
    Created:
    116 Members, 11 Topics, Public Archives, Last Post:
  • Tech: Privileged Architecture Standing Committee
    ********************************** Privileged Architecture Task Group ********************************** *Charter* : The Privileged Architecture Task Group's charter is to define and facilitate the ratification of a Privileged Architecture Specification suitable for embedded systems and Unix-like operating systems.
    Created:
    200 Members, 68 Topics, Public Archives, Last Post:
  • Tech: Profiles Group
    Technical group working on profiles.
    Created:
    18 Members, 2 Topics, Public Archives, Last Post:
  • Tech: Programming Environments
    Programming Environments Mailing list for the RISC-V toolchain efforts.
    Created:
    12 Members, 0 Topics, Public Archives
  • Tech: Reliability, availability and serviceability (RAS)
    In order to promote development of RISC-V in server domain, we need a complete specification to guide implementation of RAS in the design of SoC, firmware and OS. Tasks in scope include: RAS terminology interpretation: Interpretation of RAS concept and terminology (e.g. diagnosability, recoverability, types of error). RAS framework design: A framework covers the full path of error handling: * Error recording: Standard error record formats (e.g. register banks, APEI¡­) * Error reporting: Error event reporting methods (e.g. exceptions, NMI, local/global interrupts) * Error recovery: strategies adopted to handle the error (e.g. neglect/warning/recover/isolation/halt) RAS feature support: Engage specific RAS features into the framework: * E2E Data protection * error isolation * data poisoning containment; * advanced error reporting for PCIe
    Created:
    6 Members, 0 Topics, Public Archives
  • Tech: Processor Trace Task Group
    Processor Trace Task Group The group shall standardize both a hardware interface to the RISCV core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors. The interfaces are to provide enough information for: Instruction Trace.  The interfaces should be suitable for in-order and out-of-order cores with extensions.  The group will standardize the data format for: Compressed branch trace so that program flow can be reconstructed by debugging tools.   The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.
    Created:
    108 Members, 65 Topics, Public Archives, Last Post:
  • Tech: UNIX-Class Platform Specification Task Group
    UNIX-Class Platform Specification Task Group *Charter* : manage the UNIX-class platform specification. This working group will start by defining a subset of this platform specification that both allows compatibility with existing implementations and extensibility for the future needs
    Created:
    108 Members, 41 Topics, Public Archives, Last Post:
  • Tech: Unprivileged Architecture Standing Committee
    ************************************ Unprivileged Architecture Task Group ************************************
    Created:
    18 Members, 2 Topics, Public Archives, Last Post:
  • Tech: Vector Extension Task Group
    The V Extension Task Group is tasked with developing the specification for the RISC-V base V vector extension, including written documentation, executable model, and compliance suite.  The group is also responsible for outlining how future vector extensions can build on this baseline.
    Created:
    257 Members, 106 Topics, Public Archives, Last Post:
  • Tech: Verticals Standing Committee
    Technical Verticals Standing Committee
    Created:
    6 Members, 1 Topic, Public Archives, Last Post:
  • Tech: Virtual Memory Task Group
    Virtual Memory Task Group ------------------------- Chair: Daniel Lustig Vice Chair: Ajay Ingle Charter The goal of the Virtual Memory Task Group is to improve RISC-V support for large scale virtual memory systems.  Tasks in scope include: adding a page table format supporting 64KiB pages and larger address spaces, filling in gaps in the specification of TLB synchronization, and adding a PMA/PMP alternative that encodes coherence/cache-ability by virtual address rather than physical address.
    Created:
    120 Members, 76 Topics, Public Archives, Last Post:
  • Tech: Zfinx Task Group
    Charter The Zfinx task group will specify how to share the integer (X) registers with the floating point (F) registers, specifically to save silicon area. The group will specify the requirements for the ISA, ABI and the toolchain. The charter covers RV32 and RV64 implementations with D (64-bit), F (32-bit) and H (16-bit) floating point registers. RV128 and Q(128-bit) are considered out of scope, but should be resolvable as a simple extension to the final specification. Deliverables 1. A complete specification of Zfinx for inclusion in the RISC-V ISA manual Roadmap 1. Completely specify F-in-X (RV32F with Zfinx) and D-in-X (RV64D with Zfinx) 2. Extend to RV64F, RV64H, RV32H i.e. cases where XLEN > FLEN 3. Extend to RV32D, the only supported case where XLEN < FLEN
    Created:
    40 Members, 27 Topics, Public Archives, Last Post:
  • Trace & Debug Standing Committee
    Trace & Debug Standing Committee
    Created:
    24 Members, 8 Topics, Public Archives, Last Post:

Program Commitee

RISC-V Workshops Program Committee

  • RISC-V Program Committee for Workshops
    The Program Committee for Workshops is responsible for guiding the content and supporting/advising on the organization of  RISC-V Workshops.
    Created:
    26 Members, 56 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Program Committee for Workshops in Chennai
    RISC-V Program Committee for Workshops in Chennai
    Created:
    10 Members, 0 Topics, Archives Viewable Only By Members
  • RISC-V Program Committee for Workshops in Shanghai
    RISC-V Program Committee for Workshops in Shanghai
    Created:
    13 Members, 2 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Program Committee for RISC-V Summit
    RISC-V Program Committee for RISC-V Summit
    Created:
    15 Members, 14 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Marketing Committee

RISC-V Marketing Committee

  • RISC-V Marketing Committee
    Welcome to the RISC-V Marketing Committee. In this section you will find a calendar for upcoming meetings along with  documentation relating to our efforts to drive awareness and outbound messaging on RISC-V. Chair: Ted Marena Vice-Chair: Michael Gielda
    Created:
    237 Members, 757 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Marketing Asia Pacific Regional Task Group
    Promote awareness, learning and adoption of the RISC-V ISA in the Asia Pacific Region.
    Created:
    53 Members, 89 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Marketing Committee Task Group Chairs & Vice Chairs
    RISC-V Marketing Committee Task Group Chairs & Vice Chairs
    Created:
    13 Members, 12 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Marketing Content Task Group
    The aim of Marketing Content Task Group is to drive the content creation and curation efforts for RISC-V marketing, making sure that relevant information is available, well presented, clear and comprehensive. The Content TG recommends activities related to e.g. the RISC-V website, newsletters, training material, and the Foundation's internal communication.
    Created:
    43 Members, 216 Topics, Archives Viewable Only By Members, Last Post:
  • RISC-V Marketing Events Task Group
    RISC-V Marketing Events Task Group
    Created:
    78 Members, 170 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Marketing Committee - Embedded World Task Group
    RISC-V Marketing Committee - Embedded World Task Group Chair: Jo Windel Vice-Chair: Kevin McDermott
    Created:
    31 Members, 212 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • RISC-V Marketing Local Event Leads
    RISC-V meetup leads
    Created:
    24 Members, 5 Topics, Archives Viewable By Parent Group, Last Post:
  • RISC-V Marketing Research Task Group
    Charter 1. Identify targeted market research on RISC-V which would be of interest to the RISC-V membership at large. 2. Facilitate and support research by 3rd party analyst firms on selected topics. 3. In conjunction with Racepoint and RISC-V International staff, liaise with market researchers and analysts who are preparing RISC-V related reports. (Note: At this time, it is anticipated that the targeted research will not be funded or sponsored by the foundation or by member sponsorships. Rather, the resulting reports will be offered for a fee by the research organizations).
    Created:
    17 Members, 21 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Board of Directors

Board-level discussions

  • RISC-V Board of Directors
    RISC-V Board of Directors
    Created:
    23 Members, 675 Topics, Archives Viewable Only By Members, Restricted, Last Post:
  • China Advisory Committee
    Building on the RISC-V Foundation’s growing footprint in China across more than 25 organizations and universities, the China Advisory Committee will guide the RISC-V Foundation’s education and adoption strategies to further accelerate the RISC-V ecosystem in the region. Participation in this committee is open to foundation members who have significant China-based operations.
    Created:
    7 Members, 2 Topics, Archives Viewable Only By Members, Restricted, Last Post:

Special Interest Groups

  • Special Interest Group: Academia and Training
    ********************************************* Special Interest Group: Academia and Training ********************************************* The goal of this task group is to coordinate outreach to the open source community as well as researchers and educators in academia, and to curate and recommend training materials to both academics and professional training organizations. Note that this internal group also has a correspondence with the public group riscv-teach@riscv.org ( https://groups.google.com/a/groups.riscv.org/forum/#!forum/riscv-teach ) for non-members. The repository for educational materials is public on github ( https://github.com/riscv/educational-materials )
    Created:
    56 Members, 100 Topics, Archives Viewable Only By Members, Last Post:
  • Special Interest Group: High-Performance Computing (HPC)
    Special Interest Group: High-Performance Computing (HPC) This group is for discussions around HPC related to RISC-V
    Created:
    98 Members, 8 Topics, Archives Viewable By Parent Group, Last Post:
  • Special Interest Group: Japan
    Japan Special Interest Group
    Created:
    4 Members, 0 Topics, Archives Viewable By Parent Group
  • Special Interest Group: Functional Safety
    The RISC-V Foundation Functional Safety Special Interest Group
    Created:
    63 Members, 43 Topics, Public Archives, Last Post:
  • Special Interest Group: Soft CPU
    Soft CPU Special Interest Group
    Created:
    40 Members, 2 Topics, Archives Viewable By Parent Group, Last Post:

Technical Archives

Technical Archives

  • RISC-V Security Standing Committee MEMBERS ARCHIVE prior to Jan 2020 locked
    *Member Only List* Please use security@lists.riscv.org for public discussion. RISC-V Security Standing Committee Main Goals: ● Promote RISC-V as an ideal vehicle for the security community ● Liaise with other internal RISC V committees and with external security committees ● Create an information repository on new attack trends, threats and countermeasures ● Identify top 10 open challenges in security for the RISC-V community to address ● Propose security committees (Marketing or Technical) to tackle specific security topics ● Recruit security talent to the RISC-V ecosystem (e.g., into committees) ● Develop consensus around best security practices for IoT devices and embedded systems
    Created:
    118 Members, 298 Topics, Archives Viewable Only By Members, Last Post:
  • Tech: General Technical Discussions MEMBERS ARCHIVE prior to Jan 2020 locked
    *Members Only Archive* For public discussion please use tech@lists.riscv.org Welcome to the RISC-V Technical Discussion List. In this section of the RISC-V Foundation workspace you will find meeting minutes, showings, reports, schedules, and project descriptions compiled by the Technical Committee, updated on a regular basis. Some areas are under construction, awaiting further developments, but all areas are included to indicate the future direction of the site. Access to this area is restricted to members of the Technical Committee (primary/alternate/observer) and the Board of Directors. Please keep watching this space for new information and developments.
    Created:
    577 Members, 150 Topics, Archives Viewable Only By Members, Last Post:
  • Tech: OpCode Space Management Task Group MEMBERS ARCHIVE prior to Jan 2020 locked
    *Members only archive* The OpCode Space Management Task Group is a standing group with the task of allocating reserved opcode space for new proposed standard extensions.  The group works with task groups developing new standard extensions to avoid conflicts with other current and planned future extensions.
    Created:
    25 Members, 3 Topics, Archives Viewable Only By Members, Last Post:
  • Tech: Software Task Group MEMBERS ARCHIVE prior to Jan 2020 locked
    *Members Only Archive* Please use tech-toolchain for public discussion. Welcome to the Software Task Group. The goal of this task group is to coordinate efforts to build the RISC-V software ecosystem and to standardize RISC-V software interfaces.
    Created:
    118 Members, 72 Topics, Archives Viewable Only By Members, Last Post:
  • Tech: Vector Extension Task Group MEMBERS ARCHIVE prior to Jan 2020 locked
    *Members only archive* Please use tech-vector-ext for all public conversations The V Extension Task Group is tasked with developing the specification for the RISC-V base V vector extension, including written documentation, executable model, and compliance suite.  The group is also responsible for outlining how future vector extensions can build on this baseline.
    Created:
    187 Members, 265 Topics, Archives Viewable Only By Members, Last Post:
  • All Members
    ************************ RISC-V All-Members Group ************************ Welcome to the RISC-V Members group server! The subgroups here are moderated, members-only discussions related to the development of the RISC-V ISA. The primary website for the RISC-V architecture is at https://riscv.org. To become a member of the RISC-V Foundation community, please see https://riscv.org/membership-application The groups on this server are currently restricted to members who have signed the membership agreement. There is also a set of public mailing lists that does not require membership - you can join these discussions here: https://groups.google.com/a/groups.riscv.org This server provides discussion lists, calendars, and other services for RISC-V members, including: * technical working groups (tech-*) * marketing working groups (mktg-*) * special interest discussion groups (sig-*) * administrative groups This group " allmem " is for announcements to all members. Traffic on this list is extremely low. Discussions take place in other groups - you can view and join these subgroups by clicking "Subgroups" on the left side of this screen. Within each group, after joining the group, you can view Messages , Calendar , Files , and Wiki using the links on the left side. You can return to the main group by clicking " Your groups " at the top and choosing " RISC-V main group ", and you can view server-wide information by clicking the RISCV text at the very top left of the screen. You can subscribe to each group's calendar individually, but most people find it easier to subscribe to all of your subgroup calendars at once. Click RISCV and then Your Calendar to view or subscribe to a compilation of all of the calendars for the subgroups to which you are subscribed. To subscribe, scroll to the bottom of a calendar page, click " Subscribe to Calendar ", make a copy of the iCalendar URL and subscribe (not import) using your calendar software. Note that some users of Outlook have described time zone issues with iCalendar links, so please double-check meeting times. Finally, for every group, you can choose whether your profile is visible to others. By default, your profile is not visible. To make it visible, click your name in the upper right corner and choose " My Account ", then click the Identity tab. You can customize your profile for each group you are subscribed to. Changes made to your account profile will automatically apply to each group profile, with the exception of those specific fields in each group profile that you've previously customized.
    Created:
    1280 Members, 115 Topics, Archives Viewable Only By Members, Last Post:
  • RISC-V Ambassadors
    RISC-V Ambassadors ( https://riscv.org/risc-v-ambassadors/ )
    Created:
    12 Members, 7 Topics, Archives Viewable By Parent Group, Restricted, Last Post:
  • Tech: Trusted Execution Environment Task Group
    **************************************** Trusted Execution Environment Task Group ****************************************
    Created:
    252 Members, 104 Topics, Public Archives, Last Post: