Date   

Re: Code speed / code size groups to merge: code speed meeting on 1 Feb canceled

Tariq Kurd
 

The meeting is at 7am pacific time (you listed UK time by accident).

Tariq

-----Original Message-----
From: Jeremy Bennett [mailto:jeremy.bennett@embecosm.com]
Sent: 29 January 2021 17:42
To: sig-code-speed@lists.riscv.org
Cc: Nidal Faour <Nidal.Faour@wdc.com>; Tariq Kurd <tariq.kurd@huawei.com>; Wei Wu <wuwei2016@iscas.ac.cn>
Subject: Code speed / code size groups to merge: code speed meeting on 1 Feb canceled

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

As many of you know, we have realized that the work of the code size reduction TG and code speed optimization SIG overlaps heavily. We have therefore decided to merge the code speed optimization SIG into the code size reduction TG to create a new code optimization group.

Meetings of the code speed optimization SIG are suspended, and there will thus be no meeting next Monday, 1 February 2021.

The code optimization group will meet weekly on Tuesdays at 15:00 Pacific Time. Meetings will alternative between focusing on optimization using ISA extensions and optimization using software tool chains.

The new group will be chaired by Tariq Kurd of Huawei, who will lead the meetings focusing on ISA extensions. The vice-chair/co-chair will be Nidal Faour of Western Digital, who will lead the meetings focusing on software tool chains. Wei Wu and I as outgoing chair/co-chair of the code speed optimization SIG will become active participants in the new optimization group, providing support to Tariq and Nidal.

The next meeting of this group on Tuesday 2 February, led by Nidal, will be setting priorities for work on software tool chain optimization. This discussion will be informed by the priority list created in the code speed optimization SIG:

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

This group has a broad remit. Priority will be given to initiatives which members of the group are willing to step forward and lead.

We look forward to seeing you all at future meetings of the combined group.

Best wishes,


Jeremy Bennett, Outgoing chair, code speed optimization SIG Wei Wu, Outgoing co-chair, code speed optimization SIG

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
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Code speed / code size groups to merge: code speed meeting on 1 Feb canceled

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

As many of you know, we have realized that the work of the code size
reduction TG and code speed optimization SIG overlaps heavily. We have
therefore decided to merge the code speed optimization SIG into the
code size reduction TG to create a new code optimization group.

Meetings of the code speed optimization SIG are suspended, and there
will thus be no meeting next Monday, 1 February 2021.

The code optimization group will meet weekly on Tuesdays at 15:00
Pacific Time. Meetings will alternative between focusing on
optimization using ISA extensions and optimization using software tool
chains.

The new group will be chaired by Tariq Kurd of Huawei, who will lead
the meetings focusing on ISA extensions. The vice-chair/co-chair will
be Nidal Faour of Western Digital, who will lead the meetings focusing
on software tool chains. Wei Wu and I as outgoing chair/co-chair of
the code speed optimization SIG will become active participants in the
new optimization group, providing support to Tariq and Nidal.

The next meeting of this group on Tuesday 2 February, led by Nidal,
will be setting priorities for work on software tool chain
optimization. This discussion will be informed by the priority list
created in the code speed optimization SIG:

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

This group has a broad remit. Priority will be given to initiatives
which members of the group are willing to step forward and lead.

We look forward to seeing you all at future meetings of the combined
group.

Best wishes,


Jeremy Bennett, Outgoing chair, code speed optimization SIG
Wei Wu, Outgoing co-chair, code speed optimization SIG

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Re: [RISC-V] [tech-code-size] Optimisation group - code size / code speed combined -meetings are WEEKLY, same time as code-size

Tariq Kurd
 

I’ve fixed the calendar reminder, so you should all be able to see it now.

 

I’ve called it “Code optimisation group” following David’s suggestion.

 

Tariq

 

From: tech-code-size@... [mailto:tech-code-size@...] On Behalf Of ds2horner@...
Sent: 26 January 2021 17:50
To: tech-code-size@...; Tariq Kurd <tariq.kurd@...>; sig-code-speed@...
Subject: Re: [RISC-V] [tech-code-size] Optimisation group - code size / code speed combined -meetings are WEEKLY, same time as code-size

 

 

On 2021-01-26 12:24 p.m., Tariq Kurd via lists.riscv.org wrote:

Hi everyone,

 

We’re going to try and combine the code-size and code-speed groups,

I am not at all adverse to this.

to reduce meeting fatigue.

There are many other tangible benefits.

Inevitably ISA changes will need to be reconciled and code size and speed enhancements often compete.

I hope both groups were looking to find win-wins, but under a single umbrella we get closer.

Code optimizations with RVI are that kind of win-win, so I agree we can cooperate as a single group, at least initially while we harvest low lying fruit.

I’ve changed the code-size meetings to be “optimisation group”

what's in a name? - Shakespeare,  but isn't it too generic.

What of "code optimization" (as opposed to process, interrupt, etc. that all look to optimize for something.

and are WEEKLY on a Tuesday, at 7am California time, so the same meeting slot that we use for code-size.

è Pick a spelling, any spelling of optimi[sz]ation J

 

This is experimental at the moment, and I’m cross posting this to both mailing lists.

 

We will use the same meeting slot for all the size/speed and compiler optimisation.

 

At the meeting next week we will discuss compiler optimisation

-          Nidal will present a list of compiler optimisation tasks

-          We will discuss how to get them to happen

 

We have an existing list here:

 

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

 

and there are others listed on the code-size github page

 

the following week we will talk about code-size ISA again, and see how it goes.

 

If it’s working then we can look at officially changing to the new group, but I’d like to hold off on doing that for a few weeks until we have a better idea of how it’s going.

 

So please attend next week, and we’ll talk about compiler optimisation

 

Tariq

 

Tariq Kurd

Processor Design I RISC-V Cores, Bristol

E-mail: Tariq.Kurd@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Aztec West, Bristol, UK, BS32 4TR

315px-Huawei    http://www.huawei.com

This e-mail and its attachments contain confidential information from HUAWEI, which is intended only for the person or entity whose address is listed above. Any use of the information contained herein in any way (including, but not limited to, total or partial disclosure,reproduction, or dissemination) by persons other than the intended recipient(s) is prohibited. If you receive this e-mail in error, please notify the sender by phone or email immediately and delete it !

本邮件及其附件含有华为公司的保密信息,仅限于发送给上面 地址中列出的个人或群组。禁止任何其他人以任何形式使用(包括但不限于全部或部分地泄露、复制、或散发)本邮件中的信息。如果您错收了本邮件,请您立即电话或邮件通知发件人并删除本邮件!

 


Re: [RISC-V] [tech-code-size] Optimisation group - code size / code speed combined -meetings are WEEKLY, same time as code-size

ds2horner@...
 


On 2021-01-26 12:24 p.m., Tariq Kurd via lists.riscv.org wrote:

Hi everyone,

 

We’re going to try and combine the code-size and code-speed groups,

I am not at all adverse to this.

to reduce meeting fatigue.

There are many other tangible benefits.

Inevitably ISA changes will need to be reconciled and code size and speed enhancements often compete.

I hope both groups were looking to find win-wins, but under a single umbrella we get closer.

Code optimizations with RVI are that kind of win-win, so I agree we can cooperate as a single group, at least initially while we harvest low lying fruit.

I’ve changed the code-size meetings to be “optimisation group”

what's in a name? - Shakespeare,  but isn't it too generic.

What of "code optimization" (as opposed to process, interrupt, etc. that all look to optimize for something.

and are WEEKLY on a Tuesday, at 7am California time, so the same meeting slot that we use for code-size.

è Pick a spelling, any spelling of optimi[sz]ation J

 

This is experimental at the moment, and I’m cross posting this to both mailing lists.

 

We will use the same meeting slot for all the size/speed and compiler optimisation.

 

At the meeting next week we will discuss compiler optimisation

-          Nidal will present a list of compiler optimisation tasks

-          We will discuss how to get them to happen

 

We have an existing list here:

 

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

 

and there are others listed on the code-size github page

 

the following week we will talk about code-size ISA again, and see how it goes.

 

If it’s working then we can look at officially changing to the new group, but I’d like to hold off on doing that for a few weeks until we have a better idea of how it’s going.

 

So please attend next week, and we’ll talk about compiler optimisation

 

Tariq

 

Tariq Kurd

Processor Design I RISC-V Cores, Bristol

E-mail: Tariq.Kurd@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Aztec West, Bristol, UK, BS32 4TR

315px-Huawei    http://www.huawei.com

This e-mail and its attachments contain confidential information from HUAWEI, which is intended only for the person or entity whose address is listed above. Any use of the information contained herein in any way (including, but not limited to, total or partial disclosure,reproduction, or dissemination) by persons other than the intended recipient(s) is prohibited. If you receive this e-mail in error, please notify the sender by phone or email immediately and delete it !

本邮件及其附件含有华为公司的保密信息,仅限于发送给上面 地址中列出的个人或群组。禁止任何其他人以任何形式使用(包括但不限于全部或部分地泄露、复制、或散发)本邮件中的信息。如果您错收了本邮件,请您立即电话或邮件通知发件人并删除本邮件!

 


Optimisation group - code size / code speed combined -meetings are WEEKLY, same time as code-size

Tariq Kurd
 

Hi everyone,

 

We’re going to try and combine the code-size and code-speed groups, to reduce meeting fatigue.

I’ve changed the code-size meetings to be “optimisation group” and are WEEKLY on a Tuesday, at 7am California time, so the same meeting slot that we use for code-size.

è Pick a spelling, any spelling of optimi[sz]ation J

 

This is experimental at the moment, and I’m cross posting this to both mailing lists.

 

We will use the same meeting slot for all the size/speed and compiler optimisation.

 

At the meeting next week we will discuss compiler optimisation

-          Nidal will present a list of compiler optimisation tasks

-          We will discuss how to get them to happen

 

We have an existing list here:

 

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

 

and there are others listed on the code-size github page

 

the following week we will talk about code-size ISA again, and see how it goes.

 

If it’s working then we can look at officially changing to the new group, but I’d like to hold off on doing that for a few weeks until we have a better idea of how it’s going.

 

So please attend next week, and we’ll talk about compiler optimisation

 

Tariq

 

Tariq Kurd

Processor Design I RISC-V Cores, Bristol

E-mail: Tariq.Kurd@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Aztec West, Bristol, UK, BS32 4TR

315px-Huawei    http://www.huawei.com

This e-mail and its attachments contain confidential information from HUAWEI, which is intended only for the person or entity whose address is listed above. Any use of the information contained herein in any way (including, but not limited to, total or partial disclosure,reproduction, or dissemination) by persons other than the intended recipient(s) is prohibited. If you receive this e-mail in error, please notify the sender by phone or email immediately and delete it !

本邮件及其附件含有华为公司的保密信息,仅限于发送给上面 地址中列出的个人或群组。禁止任何其他人以任何形式使用(包括但不限于全部或部分地泄露、复制、或散发)本邮件中的信息。如果您错收了本邮件,请您立即电话或邮件通知发件人并删除本邮件!

 


Draft GNU tool chain sign off criteria

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

I've taken the document from Code Size Reduction TG and morphed it
into a draft RISC-V policy:

https://docs.google.com/document/d/1Eio39QTHNM9Lmi1VXoH7PYLgBGUscvpdPxB6YmZonVk

Scheduled for review at T&R on Thursday 14 January. Apologies for
cross-posting, but wanted to pick up everyone who has contributed so far.

Best wishes,


Jeremy

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Re: FYI: The assignment process with the FSF for PLCT Lab is complete

Tariq Kurd
 

That's brilliant news, well done!

Tariq

-----Original Message-----
From: sig-code-speed@lists.riscv.org [mailto:sig-code-speed@lists.riscv.org] On Behalf Of Jeremy Bennett
Sent: 05 January 2021 18:38
To: Wei Wu (吴伟) <lazyparser@gmail.com>; Jim Wilson <jimw@sifive.com>
Cc: sig-code-speed@lists.riscv.org; Yungang Bao <baoyg@ict.ac.cn>; Mark Himelstein <markhimelstein@riscv.org>
Subject: Re: [RISC-V] [sig-code-speed] FYI: The assignment process with the FSF for PLCT Lab is complete

* PGP Signed by an unknown key

On 24/12/2020 10:29, Wei Wu (吴伟) wrote:
Hi Jim and Jeremy,

Just a quick reminder that the ISCAS/PLCT has completed the copyright
assignment. Now Jiawei and all other ISCAS staff & students are able
to contribute to the GNU GCC, GDB, Binutls, and Glibc projects. Thank
you for your kind help.
Hi Wei Wu,

Happy New Year.

That's great news. Look forward to contributions from ISCAS/PLCT. Plus I hope you and your colleagues will attend the GNU Tools Cauldron meeting when it restarts.

Best wishes,


Jeremy

Happy holiday!

-- Best wishes, Wei Wu (吴伟)

--
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20

* Unknown Key
* 0xFB4754E1(L)


Minutes of Code Speed Optimization SIG 4 January 2021

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

The minutes of Monday's meeting are available in the RISC-V shared
area. Actions for everyone attending.

https://drive.google.com/file/d/1jP-aqI0EHZ4NnzYyczHiARYj9rZ--3g9

Source is in the GitHub repo:

https://github.com/riscv/riscv-code-speed-optimization/blob/main/meetings/2021-01-04-minutes.adoc

Our next meeting will be at 07:00 Pacific Time on Monday 1 February 2021.

Best wishes,


Jeremy Bennett, Chair
Wei Wu, Co-chair

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Re: FYI: The assignment process with the FSF for PLCT Lab is complete

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 24/12/2020 10:29, Wei Wu (吴伟) wrote:
Hi Jim and Jeremy,

Just a quick reminder that the ISCAS/PLCT has completed the
copyright assignment. Now Jiawei and all other ISCAS staff &
students are able to contribute to the GNU GCC, GDB, Binutls, and
Glibc projects. Thank you for your kind help.
Hi Wei Wu,

Happy New Year.

That's great news. Look forward to contributions from ISCAS/PLCT. Plus
I hope you and your colleagues will attend the GNU Tools Cauldron
meeting when it restarts.

Best wishes,


Jeremy

Happy holiday!

-- Best wishes, Wei Wu (吴伟)

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Re: Thoughts on proposing Java Speed TG and JavaScript Speed TG, and the (planned) Managed Runtime SIG/TG

Wei Wu (吴伟)
 

I'd prefer to separate into different TGs. Either Java or JavaScript language has a very large number of applications, and they have different language characteristics, different benchmarks. One TG to cover them all might to big and diverse.

On Thu, Dec 24, 2020 at 11:34 PM Mark Himelstein <markhimelstein@...> wrote:
should it just be java or should it cover any interpretated or JITed language?

--------
sent from a mobile device. please forgive any typos.

> On Dec 22, 2020, at 4:17 AM, Wei Wu <lazyparser@...> wrote:
>
> 
> Hi all,
>
> I think it is the time to create a Java Speed TG for the porting of OpenJDK/OpenJ9/OpenArkCompiler, and a TG for V8/Spidermonkey/JSC and engines for webassembly.
>
> The PLCT Lab is pushing the boundary of the RISC-V software ecosystem by speeding up the JavaScript and Java codes running on the RISC-V platform. We collaborate with FutureWei and RIOS Lab on V8 for RISC-V project, with BishengJDK (Huawei) on OpenJDK for RISC-V project. The upstreaming for V8 is near done, while the upstreaming of OpenJDK will start soon (by Yadong Wang from Huawei). We are going to speed up more than 100x for both Java and JavaScript in 2021. More collaboration among all the teams involved becomes much more important.
>
> The question I have is how to create the two TGs? Now the RVI has Software SSC, T&R subcommittee, and Code Speed Opt SIG. IIUC The code speed SIG spawns new proposals of TG and sends them to T&R subcommittee for approval.
>
> I am the co-chair of the code speed SIG, so I'm OK with the process mentioned above. What I'm not sure is the status of the Runtime SIG/TG .Two months ago, we talked about the creation of the Managed Runtime SIG/TG in the meeting/mailing list/mail threads under the Toolchain & Runtime subcommittee. I want to make sure that if anyone is preparing similar proposals before I start to write, to avoid duplicate works.
>
> Please let me know if anyone is preparing similar proposals. Thanks.
>
> --
> Best wishes,
> Wei Wu (吴伟)


--
Best wishes,
Wei Wu (吴伟)


Re: Thoughts on proposing Java Speed TG and JavaScript Speed TG, and the (planned) Managed Runtime SIG/TG

mark
 

should it just be java or should it cover any interpretated or JITed language?

--------
sent from a mobile device. please forgive any typos.

On Dec 22, 2020, at 4:17 AM, Wei Wu <lazyparser@gmail.com> wrote:


Hi all,

I think it is the time to create a Java Speed TG for the porting of OpenJDK/OpenJ9/OpenArkCompiler, and a TG for V8/Spidermonkey/JSC and engines for webassembly.

The PLCT Lab is pushing the boundary of the RISC-V software ecosystem by speeding up the JavaScript and Java codes running on the RISC-V platform. We collaborate with FutureWei and RIOS Lab on V8 for RISC-V project, with BishengJDK (Huawei) on OpenJDK for RISC-V project. The upstreaming for V8 is near done, while the upstreaming of OpenJDK will start soon (by Yadong Wang from Huawei). We are going to speed up more than 100x for both Java and JavaScript in 2021. More collaboration among all the teams involved becomes much more important.

The question I have is how to create the two TGs? Now the RVI has Software SSC, T&R subcommittee, and Code Speed Opt SIG. IIUC The code speed SIG spawns new proposals of TG and sends them to T&R subcommittee for approval.

I am the co-chair of the code speed SIG, so I'm OK with the process mentioned above. What I'm not sure is the status of the Runtime SIG/TG .Two months ago, we talked about the creation of the Managed Runtime SIG/TG in the meeting/mailing list/mail threads under the Toolchain & Runtime subcommittee. I want to make sure that if anyone is preparing similar proposals before I start to write, to avoid duplicate works.

Please let me know if anyone is preparing similar proposals. Thanks.

--
Best wishes,
Wei Wu (吴伟)


FYI: The assignment process with the FSF for PLCT Lab is complete

Wei Wu (吴伟)
 

Hi Jim and Jeremy,

Just a quick reminder that the ISCAS/PLCT has completed the copyright assignment. Now Jiawei and all other ISCAS staff & students are able to contribute to the GNU GCC, GDB, Binutls, and Glibc projects. Thank you for your kind help.

Happy holiday!

--
Best wishes,
Wei Wu (吴伟)


Code Speed Optimization SIG meeting 4 January 2021

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

The agenda for our first meeting of 2021 at 07:00 Pacific Time on
Monday 4 January is now available via GitHub:

https://github.com/riscv/riscv-code-speed-optimization/blob/main/meetings/2021-01-04-agenda.adoc

and in Google Docs "for risc-v members>subcommittees, task groups, and
SIGs>code-speed-optimization>meetings"

https://docs.google.com/presentation/d/139w4WjPHbfMiXPmtaCCL-Lf3nx9n_4HpMg7VxFd2T4s/edit?usp=sharing

We shall be finalizing the proposal for our highest priority project,
ready to request the Toolchain & Runtimes SC to create a Task Group to
manage the project:

#1 Continuous integration, testing, trace and benchmarking

We shall start detailed work on our next proposal:

#2 Compiler optimizations for the 'B extension

We look forward to seeing you there. In the meantime have a very Merry
Christmas and Happy New Year.

Best wishes,


Jeremy, Chair
Wei Wu, Co-chair

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Thoughts on proposing Java Speed TG and JavaScript Speed TG, and the (planned) Managed Runtime SIG/TG

Wei Wu (吴伟)
 

Hi all,

I think it is the time to create a Java Speed TG for the porting of OpenJDK/OpenJ9/OpenArkCompiler, and a TG for V8/Spidermonkey/JSC and engines for webassembly.

The PLCT Lab is pushing the boundary of the RISC-V software ecosystem by speeding up the JavaScript and Java codes running on the RISC-V platform. We collaborate with FutureWei and RIOS Lab on V8 for RISC-V project, with BishengJDK (Huawei) on OpenJDK for RISC-V project. The upstreaming for V8 is near done, while the upstreaming of OpenJDK will start soon (by Yadong Wang from Huawei). We are going to speed up more than 100x for both Java and JavaScript in 2021. More collaboration among all the teams involved becomes much more important.

The question I have is how to create the two TGs? Now the RVI has Software SSC, T&R subcommittee, and Code Speed Opt SIG. IIUC The code speed SIG spawns new proposals of TG and sends them to T&R subcommittee for approval.

I am the co-chair of the code speed SIG, so I'm OK with the process mentioned above. What I'm not sure is the status of the Runtime SIG/TG .Two months ago, we talked about the creation of the Managed Runtime SIG/TG in the meeting/mailing list/mail threads under the Toolchain & Runtime subcommittee. I want to make sure that if anyone is preparing similar proposals before I start to write, to avoid duplicate works.

Please let me know if anyone is preparing similar proposals. Thanks.

--
Best wishes,
Wei Wu (吴伟)


Re: [sw-dev] [CodeSpeed][Java] Now we have the first RISCV64G porting in OpenJDK11 (BishengJDK)

Wei Wu (吴伟)
 

Hi Sean,

Currently the porting is RV64G only, the RV32 porting is not done yet. For the 64-bit Fedora, Dingli has wrote a blog for it:


Hopefully the porting of RV32 would be started after the upstreaming of RV64G porting.


On Sat, Dec 19, 2020 at 6:48 AM Sean Halle <seanhalle@...> wrote:

Hi Wei, thank you and the Bisheng team for this :-)

We have been trying to build this via QEMU in Fedora 32 for RISC-V.  There are many dependencies that need to be installed, which in turn have other dependencies that are problematic, and we encountered a segfault while building.  Do you happen to have a Docker container or some other ready environment in which to build the source?  Or a downloadable binary for Fedora?

Thanks Wei,

Sean


On Mon, Nov 16, 2020 at 6:32 AM Wei Wu (吴伟) <lazyparser@...> wrote:
Hi all,

I am very excited to share this news with you. The BishengJDK team from huawei has just open sourced their initial porting for RV64G platform. Anyone who is interested is recommended to fork the code and have a try.

The official repo is here:

A github mirror has been set if you could not access the official repo:

Next steps:
- Functional Testing on physical boards. The BishengJDK team has tested on QEMU only, due to the lack of physical risc-v boards.The PLCT lab will cover these testing.
- perf baseline is going to set. The PLCT Lab will help to track all main java benchmarks.
- The BishengJDK team would start to upstream soon. (A few docs are written in non-English language which need to be translated. after this the code review would be started.)
- Further roadmap would be discussed on the code speed SIG meetings and toolchain & runtime meetings. We are inviting all contributors who are porting JDK to RISC-V join us.

--
Best wishes,
Wei Wu (吴伟)

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--
Best wishes,
Wei Wu (吴伟)


Re: [sw-dev] [CodeSpeed][Java] Now we have the first RISCV64G porting in OpenJDK11 (BishengJDK)

Sean Halle <seanhalle@...>
 


Hi Wei, thank you and the Bisheng team for this :-)

We have been trying to build this via QEMU in Fedora 32 for RISC-V.  There are many dependencies that need to be installed, which in turn have other dependencies that are problematic, and we encountered a segfault while building.  Do you happen to have a Docker container or some other ready environment in which to build the source?  Or a downloadable binary for Fedora?

Thanks Wei,

Sean


On Mon, Nov 16, 2020 at 6:32 AM Wei Wu (吴伟) <lazyparser@...> wrote:
Hi all,

I am very excited to share this news with you. The BishengJDK team from huawei has just open sourced their initial porting for RV64G platform. Anyone who is interested is recommended to fork the code and have a try.

The official repo is here:

A github mirror has been set if you could not access the official repo:

Next steps:
- Functional Testing on physical boards. The BishengJDK team has tested on QEMU only, due to the lack of physical risc-v boards.The PLCT lab will cover these testing.
- perf baseline is going to set. The PLCT Lab will help to track all main java benchmarks.
- The BishengJDK team would start to upstream soon. (A few docs are written in non-English language which need to be translated. after this the code review would be started.)
- Further roadmap would be discussed on the code speed SIG meetings and toolchain & runtime meetings. We are inviting all contributors who are porting JDK to RISC-V join us.

--
Best wishes,
Wei Wu (吴伟)

--
You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+unsubscribe@....
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CANkjrB7sxHkexe6NkCpHk-u%3DfqV0C_1SEd2hXgHE5ogrtbG-dQ%40mail.gmail.com.


Minutes of Code Speed Optimization SIG 15 Dec 2020

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

The minutes of last week's meeting are available in the RISC-V shared
area. Actions for Jeremy Bennett and Wei Wu.

https://drive.google.com/file/d/1SNk99y6C1BbEAsI15ldln-gIv7etoeep

At our next meeting we shall work on two areas

1. We shall finalize the PRD for our top priority project: continuous
integration, test, benchmarking and tracing, with a view to submitting
it to toolchains & runtimes for a task group to be created.

2. We shall discuss the PRD detail for our second priority project:
compiler and library optimizations for the 'B' extension.

Best wishes,


Jeremy

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Slides: Proposal of code speed tracking system - 1st version - 20201215

Wei Wu (吴伟)
 

Hi,

FYI The attachment is the slides I reported yesterday. Feedbacks are welcome!


--
Best wishes,
Wei Wu (吴伟)


Code Speed Optimization SIG meeting moved to Tuesday 15 December 2020

Jeremy Bennett
 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi all,

The decision has been taken to cancel/move all meetings in the week
7-11 December to avoid clashing with RISC-V summit.

We shall therefore move our meeting to 16:00 Pacific Time on Tuesday
15 December 2020. Note that this is an hour later than usual, and
follows immediately after the Code Size Reduction SIG meeting.

The agenda has been updated with the new details and is available via
GitHub:

https://github.com/riscv/riscv-code-speed-optimization/blob/main/meetings/2020-12-15-agenda.adoc

and in Google Docs "for risc-v members>subcommittees, task groups, and
SIGs>code-speed-optimization>meetings"

https://docs.google.com/presentation/d/1cmV1fuHT6IzCQU5noxGKqBB1v339fVA9EN2PQif_cQQ

We shall be preparing the initial version of our top two project
proposals:

#1 Continuous integration, testing, trace and benchmarking
#2 Compiler optimizations for upcoming extensions

We look forward to seeing you there.

Best wishes,


Jeremy, Chair
Wei Wu, Co-chair

On 04/12/2020 13:55, Jeremy Bennett wrote:


Hi all,

The agenda for our meeting at 07:00 Pacific Time on Monday 7
December is now available via GitHub:

https://github.com/riscv/riscv-code-speed-optimization/blob/main/meetings/2020-12-07-agenda.adoc

and in Google Docs "for risc-v members>subcommittees, task groups,
and SIGs>code-speed-optimization>meetings"

https://docs.google.com/presentation/d/1cmV1fuHT6IzCQU5noxGKqBB1v339fVA9EN2PQif_cQQ

We shall be preparing the initial version of our top two project
proposals:

#1 Continuous integration, testing, trace and benchmarking #2
Compiler optimizations for upcoming extensions

We look forward to seeing you there.

Best wishes,


Jeremy, Chair Wei Wu, Co-chair

- --
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jeremy.bennett@embecosm.com
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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Re: [CodeSpeed][Java] Now we have the first RISCV64G porting in OpenJDK11 (BishengJDK)

wangyadong (E) <yadonn.wang@...>
 

Hi, Alexander,

     Its a fully RV64G implementation of OpenJDK11u with the template interpreter and JIT backend (including both C1 and C2, but excluding AOT/JVMCI).

The test was started recently on the HiFive Unleashed together with Wei Wus team, and we’re also following the main line of the OpenJDK master, and will try to upstream to the community when the port’s stable.

 

Best Regards,

Yadong Wang

 

发件人: Alexander Zinovyev [mailto:zigmatulin@...]
发送时间: 2020124 17:42
收件人: RISC-V SW Dev <sw-dev@...>
抄送: lazyp...@... <lazyparser@...>; wangyadong (E) <yadonn.wang@...>; din...@... <dingli@...>; sig-cod...@... <sig-code-speed@...>
主题: Re: [RISC-V] [sig-code-speed] [CodeSpeed][Java] Now we have the first RISCV64G porting in OpenJDK11 (BishengJDK)

 

Hi Wei Wu,
  

  That is exciting. 

  Would it be possible to provide some additional information (or link to the document where it is already documented) about the scope of what was included? I'm interested in particular in JIT, TemplateInterpreter, etc. I looked at repository and I didn't find it was mentioned there, so decided to double check here.

On Monday, November 30, 2020 at 12:07:41 AM UTC+13 lazyp...@... wrote:

Hi all:

 

Java Speed Update:

 

The BishengJDK team and PLCT Lab have some initial results of BishengJDK's RV64G port.

The result is very promising. Roughly 20x improvement has been observed. We are very

optimistic on the 100x speed up goal[1].

 

We are inviting all teams, companies, or individuals who are interested in OpenJDK to join us,

as one unite open source team for OpenJDK RISC-V porting.

 

 

## Benchmark

 

SPECjvm98

 

## Platform

 

Hifive Unleashed (RV64GC), Fedora/RISCV64GC port

 

## the text format:

 

benchmark normal zero B/C*100%
startup.helloworld 15.61 10.69 146.02%
startup.compiler.compiler 15.27 10.75 142.05%
startup.compiler.sunflow 15.38 10.85 141.75%
startup.compress 3.48 0.07 4971.43%
startup.crypto.aes 0.88 0.05 1760.00%
startup.crypto.rsa 4 0.13 3076.92%
startup.crypto.signverify 4.37 0.06 7283.33%
startup.mpegaudio 1.86 0.1 1860.00%
startup.scimark.fft 4.3 0.39 1102.56%
startup.scimark.lu 2.98 0.2 1490.00%
startup.scimark.monte_carlo 3.2 0.05 6400.00%
startup.scimark.sor 3.97 0.29 1368.97%
startup.scimark.sparse 2.19 0.2 1095.00%
startup.serial 1.17 0.04 2925.00%
startup.sunflow 8.16 0.11 7418.18%
startup.xml.transform 0.18 0.02 900.00%
startup.xml.validation 2.04 0.14 1457.14%
compiler.compiler NA NA NA
compiler.sunflow NA NA NA
compress 20.85 0.27 7722.22%
crypto.aes 3.66 0.18 2033.33%
crypto.rsa 35.33 0.56 6308.93%
crypto.signverify 36.94 0.26 14207.69%
derby 1.31 NA NA
mpegaudio NA 0.39 NA
scimark.fft.large 7.22 NA NA
scimark.lu.large 0.84 NA NA
scimark.sor.large 3.24 NA NA
scimark.sparse.large 1.27 NA NA
scimark.fft.small 22.12 1.58 1400.00%
scimark.lu.small 14.57 0.81 1798.77%
scimark.sor.small 20.64 1.16 1779.31%
scimark.sparse.small 6.89 0.75 918.67%
scimark.monte_carlo 20.07 0.21 9557.14%
serial 5.85 NA NA
sunflow NA NA NA
xml.transform 15.93 NA NA
xml.validation 33.51 NA NA

 

(the attachment is the jpeg format of the result)

 

On Sat, Nov 21, 2020 at 3:46 PM Wei Wu (吴伟) via lists.riscv.org <lazyparser=gmai...@...> wrote:

Hi all,

 

Dingli Zhang from the PLCT Lab wrote a blog about how to test BishengJDK (OpenJDK) on the HiFive Unleashed board. A few bugs had been found when he wrote the article, and glad to know that engineers from the BishengJDK team have already fixed the issues (good job!). We'll post the initial benchmark results once it gets done.

 

As the previous email mentioned, the BishengJDK team is willing to push the efforts to OpenJDK upstream. The PLCT Lab is collaborating with them and united as one group to improve the RV64 backend. Anyone who is working on or willing to work on the OpenJDK/OpenJ9 is welcome and invited to join the group.

 

https://plctlab.github.io/openjdk/Building_instruction_and_test_of_BishengJDK11_on_HiFive_Unleashed.html
> BishengJDK 11 now brings the template interpreter and backends of C1/C2 compiler to the RISC-V world.
> This test is to build the JDK on RISCV64 and do some benchmark on HiFive Unleashed.

 

 

On Mon, Nov 16, 2020 at 10:31 PM Wei Wu (吴伟) <lazyp...@...> wrote:

Hi all,

 

I am very excited to share this news with you. The BishengJDK team from huawei has just open sourced their initial porting for RV64G platform. Anyone who is interested is recommended to fork the code and have a try.

 

The official repo is here:

 

A github mirror has been set if you could not access the official repo:

 

Next steps:

- Functional Testing on physical boards. The BishengJDK team has tested on QEMU only, due to the lack of physical risc-v boards.The PLCT lab will cover these testing.

- perf baseline is going to set. The PLCT Lab will help to track all main java benchmarks.

- The BishengJDK team would start to upstream soon. (A few docs are written in non-English language which need to be translated. after this the code review would be started.)

- Further roadmap would be discussed on the code speed SIG meetings and toolchain & runtime meetings. We are inviting all contributors who are porting JDK to RISC-V join us.


--

Best wishes,
Wei Wu (
吴伟)



--

Best wishes,
Wei Wu (
吴伟)



--

Best wishes,
Wei Wu (
吴伟)

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