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[RISC-V] [tech-code-size] Optimisation group - code size / code speed combined -meetings are WEEKLY, same time as code-size


ds2horner@...
 


On 2021-01-26 12:24 p.m., Tariq Kurd via lists.riscv.org wrote:

Hi everyone,

 

We’re going to try and combine the code-size and code-speed groups,

I am not at all adverse to this.

to reduce meeting fatigue.

There are many other tangible benefits.

Inevitably ISA changes will need to be reconciled and code size and speed enhancements often compete.

I hope both groups were looking to find win-wins, but under a single umbrella we get closer.

Code optimizations with RVI are that kind of win-win, so I agree we can cooperate as a single group, at least initially while we harvest low lying fruit.

I’ve changed the code-size meetings to be “optimisation group”

what's in a name? - Shakespeare,  but isn't it too generic.

What of "code optimization" (as opposed to process, interrupt, etc. that all look to optimize for something.

and are WEEKLY on a Tuesday, at 7am California time, so the same meeting slot that we use for code-size.

è Pick a spelling, any spelling of optimi[sz]ation J

 

This is experimental at the moment, and I’m cross posting this to both mailing lists.

 

We will use the same meeting slot for all the size/speed and compiler optimisation.

 

At the meeting next week we will discuss compiler optimisation

-          Nidal will present a list of compiler optimisation tasks

-          We will discuss how to get them to happen

 

We have an existing list here:

 

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

 

and there are others listed on the code-size github page

 

the following week we will talk about code-size ISA again, and see how it goes.

 

If it’s working then we can look at officially changing to the new group, but I’d like to hold off on doing that for a few weeks until we have a better idea of how it’s going.

 

So please attend next week, and we’ll talk about compiler optimisation

 

Tariq

 

Tariq Kurd

Processor Design I RISC-V Cores, Bristol

E-mail: Tariq.Kurd@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Aztec West, Bristol, UK, BS32 4TR

315px-Huawei    http://www.huawei.com

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Tariq Kurd
 

I’ve fixed the calendar reminder, so you should all be able to see it now.

 

I’ve called it “Code optimisation group” following David’s suggestion.

 

Tariq

 

From: tech-code-size@... [mailto:tech-code-size@...] On Behalf Of ds2horner@...
Sent: 26 January 2021 17:50
To: tech-code-size@...; Tariq Kurd <tariq.kurd@...>; sig-code-speed@...
Subject: Re: [RISC-V] [tech-code-size] Optimisation group - code size / code speed combined -meetings are WEEKLY, same time as code-size

 

 

On 2021-01-26 12:24 p.m., Tariq Kurd via lists.riscv.org wrote:

Hi everyone,

 

We’re going to try and combine the code-size and code-speed groups,

I am not at all adverse to this.

to reduce meeting fatigue.

There are many other tangible benefits.

Inevitably ISA changes will need to be reconciled and code size and speed enhancements often compete.

I hope both groups were looking to find win-wins, but under a single umbrella we get closer.

Code optimizations with RVI are that kind of win-win, so I agree we can cooperate as a single group, at least initially while we harvest low lying fruit.

I’ve changed the code-size meetings to be “optimisation group”

what's in a name? - Shakespeare,  but isn't it too generic.

What of "code optimization" (as opposed to process, interrupt, etc. that all look to optimize for something.

and are WEEKLY on a Tuesday, at 7am California time, so the same meeting slot that we use for code-size.

è Pick a spelling, any spelling of optimi[sz]ation J

 

This is experimental at the moment, and I’m cross posting this to both mailing lists.

 

We will use the same meeting slot for all the size/speed and compiler optimisation.

 

At the meeting next week we will discuss compiler optimisation

-          Nidal will present a list of compiler optimisation tasks

-          We will discuss how to get them to happen

 

We have an existing list here:

 

https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/candidate-projects.adoc

 

and there are others listed on the code-size github page

 

the following week we will talk about code-size ISA again, and see how it goes.

 

If it’s working then we can look at officially changing to the new group, but I’d like to hold off on doing that for a few weeks until we have a better idea of how it’s going.

 

So please attend next week, and we’ll talk about compiler optimisation

 

Tariq

 

Tariq Kurd

Processor Design I RISC-V Cores, Bristol

E-mail: Tariq.Kurd@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Aztec West, Bristol, UK, BS32 4TR

315px-Huawei    http://www.huawei.com

This e-mail and its attachments contain confidential information from HUAWEI, which is intended only for the person or entity whose address is listed above. Any use of the information contained herein in any way (including, but not limited to, total or partial disclosure,reproduction, or dissemination) by persons other than the intended recipient(s) is prohibited. If you receive this e-mail in error, please notify the sender by phone or email immediately and delete it !

本邮件及其附件含有华为公司的保密信息,仅限于发送给上面 地址中列出的个人或群组。禁止任何其他人以任何形式使用(包括但不限于全部或部分地泄露、复制、或散发)本邮件中的信息。如果您错收了本邮件,请您立即电话或邮件通知发件人并删除本邮件!