Re: [RISC-V] [tech-unixplatformspec] [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
On Fri, Jul 16, 2021 at 10:32 PM Greg Favor via lists.riscv.org <gfavor=ventanamicro.com@...> wrote:
Lastly, before I shut up, ...
A key point in all this is that memory-mapped registers like MTIME/MTIMECMP will be very uncommon. Most registers, even if logically defined as 64 bits wide, can be readily accessed by software using one or a pair of 32-bit accesses.
Especially since those 64-bit registers can only be accessed using 32-bit accesses in RV32 systems, arch definitions of such registers will be motivated to avoid causing complications for RV32 systems where at all possible.