Application and Tools Horizontal Committee (HC) Welcome to the App & Tools HC. The goal of this task group is to coordinate efforts to build the RISC-V software ecosystem and to standardize RISC-V software interfaces.

RISC-V Development Partners This group is dedicated to providing support for specification development by providing engineering resources to help get the specification tasks done for ratification.  Activities are tracked in the development partner status spreadsheet ( https://docs.google.com/spreadsheets/d/1_JXyCZWKgyeofnz8oYTd8AwZC7An8-6-NOPsiqGLTNs/ ). If you're interested in becoming a development partner please email us at help@riscv.org.

The ISA Infrastructure HC coordinates efforts of SIGs that are not ISA but are needed for ISA development. This includes: * Architectural Compatibility Tests to ensure vendor implementations are ISA compatible, * Simulators to provide references for compatibility, * Continuous Integration to ensure changes to tests, simulators, and tools don’t break existing code, * Devops for computing resources needed for the above, and * Documentation to communicate ISA development.

Welcome to the Privileged Software list. This lists has content related to work groups that fall under the Privileged SW HC umbrella. Expect announcements and other communications about all things related to privileged software (fw, kernel, etc).

RISC-V Security Horizontal Committee Main Goals: ● Promote RISC-V as an ideal vehicle for the security community ● Liaise with other internal RISC V committees and with external security committees ● Create an information repository on new attack trends, threats and countermeasures ● Identify top 10 open challenges in security for the RISC-V community to address ● Propose security committees (Marketing or Technical) to tackle specific security topics ● Recruit security talent to the RISC-V ecosystem (e.g., into committees) ● Develop consensus around best security practices for IoT devices and embedded systems

This mailing list is devoted to fostering insightful discussions on mapping diverse segments to their respective RISC-V profiles, with a focus on achieving optimal alignment and organization

Welcome to the SOC Infrastructure Horizontal Committee. The SOC infrastructure Horizontal committee contains but not limited to the components that straddle the hardware/software boundary and are necessary to boot and operate systems in every product from IOT/embedded through Data Center/Cloud and beyond. By their nature these components are also often matrixed into other committees pertaining to security, RAS, platforms, etc. The intent is to provide a robust set of specifications that product implementer's need to be successful while minimizing duplication of effort and fragmentation of design choices in the RISC-V community. Presentations and materials discussed during HC meetings are placed here: https://drive.google.com/drive/folders/13wsg46NjLr4pmEgMNqjDr6hNlAw3knAG

Welcome to the RISC-V Technical discussion list.

Advanced Interrupt Architecture (AIA) SIG

Technical announcements only (no discussions)

The RISC-V Application Platform - Trusted Execution Environment Task Group (AP-TEE TG) will collaborate to define the reference architecture for confidential computing on RISC-V platforms - including the ABI required to enable systems software to manage confidential workloads on a multi-tenant platform, while keeping the OS/hypervisor and entities that develop the OS/VMM and/or operate/manage the platform outside the TCB. The TG will design the interfaces to comprehend existing (ratified) ISA and ensure extensibility of the interfaces to new Architectural ISA extensions as required for security or performance of confidential workloads. In addition to the normative specifications mentioned, the TG will produce a security architecture analysis per the threat model agreed upon as a living (non-normative) document supporting security recommendations, implementation-specific guidelines and relevant standard protocols for attestation for implementers of the AP-TEE capability on their RISC-V platforms. Spec github: link ( https://github.com/riscv-non-isa/riscv-ap-tee ) Shared Folder for meetings: link ( https://drive.google.com/drive/folders/152uwh6fjvHvarFCuTce-AhNTJ58Bh3k2 )

The AP-TEE-IO community is a place for discussing, enabling and developing trusted I/O on RISC-V based SoCs. This includes, but is not limited to, device attachment to Trusted Execution Environments based on the RISC-V AP-TEE specifications.

This email list is for submitting proposed extensions for review as well for getting help and guidance. All proposed extensions (including FastTrack) must receive approval from the review prior to Freeze Milestone. The review includes: * Specification - clarity and completeness * Instructions - utility and value * Opcodes - utility and value (allocated upon approval) * State - utility and value (allocated upon approval) * Mnemonics - clarity and consistency * Sub-extension strings - clarity and consistency

*********************** *Base ISA Ratification* *********************** *Charter* : To define, specify, and ratify the unprivileged RISC-V base architectures and standard extensions.

The Capacity and Bandwidth controller QoS Register Interface (CBQRI) TG will develop a standard register interface for configuring resource allocations into resource controllers and to enable resource usage monitoring in such controllers. QRI enables a uniform view of configuring and controlling the resource controllers and eases product integration and software enabling/support.

*** This is an "invite only" group to which one gets invited when they become a Chair or a Vice-chair of working group (HC, IC, SIG, TG). *** Questions about membership can be raised via email to help@riscv.org.

*Code Size Reduction Task Group* *Chair* : Tariq Kurd tariq.kurd@huawei.com ( tariq.kurd@huawei.com ) *Vice-chair* Nidal Faour Nidal.Faour@wdc.com ( Nidal.Faour@wdc.com ) *Charter* The code size reduction TG will develop a holistic solution to reducing code size, covering different profiles to be competitive with other core implementations of other architectures of a similar class. Priority is given to small embedded cores which often have very constrained memory sizes and so code size reduction is most important for cost reduction. Larger/higher performance cores will also benefit from reduced code size. *Output* The output will be improved toolchain technology to reduce code size, and also at least one ISA extension to reduce code size with toolchain support in both GCC and LLVM. If any part of any future ISA extension risks complicating the design of high performance cores, then those instructions will be in a different subset so that they can be excluded. Therefore high performance cores will also benefit from improved toolchain technology and also an ISA extension. Output from the TG could include coding recommendations to improve code size. *Initial Roadmap* - Build a benchmark / application suite for measuring code size - Collect existing proposals for code size reduction ISA extensions - I mprove compiler support in known weak areas, such as function call prologue/epilogue - Add a new code size reduction ISA extension using encodings in line with the Instruction Encoding Allocation Policy, to address cases where the toolchain improvements alone cannot solve the code size problem *Other TGs* This TG will handle all aspects of making RISC-V code-size competitive.  CMO, B-extension, Zfinx, EABI, Fast Interrupts and the J-extension all already have related work, but other tasks groups may as well so this is not a complete list. New TGs may be spawned as required to complete the objective. The TG will report to the software standing committee, and will work with the unprivileged standing committee to ratify any ISA extensions.

Unified Discovery Task Group github: https://github.com/riscv/configuration-structure

Will craft a specification for an extension to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

*********************************** Cryptographic Extensions Task Group *********************************** The Cryptographic Extensions Task Group will propose ISA extensions to the vector extensions for the standardized and secure execution of popular cryptography algorithms.  To ensure that processor implementers are able to support a wide range of performance and security levels the committee will create a base and an extended specification. The base will be comprised of low-cost instructions that are useful for the acceleration of common algorithms. The extended specification will include greater functionality, reserve encodings for more algorithms, and will facilitate improved security of execution and higher performance.   The scope will include symmetric and asymmetric cryptographic algorithms and related primitives such as message digests.  The committee will also make ISA extension proposals for lightweight scalar instructions for 32 and 64 bit machines that improve the performance and reduce the code size required for software execution of common algorithms like AES and SHA and lightweight algorithms like PRESENT and GOST, as well as ISA proposals regarding the use of random bits and secure key management.

Community will develop an optional ISA extension for specific Russian national symmetric cryptography ("Kuznyechik", "Magma", and "Streebog") on both RV32 and RV64. The deliverables match CETG Definition-of-Done: Technical rationale, ISA definitions, specification document, architectural compatibility tests, SAIL, opcode allocation, compiler support.

**************** Debug Task Group **************** Welcome to the RISC-V Debug Task Group. The Debug Task Group's goal is the creation of tasks groups which create specifications concerning for how to enable low-level hardware debugging on RISC-V implementations.

************************* Fast Interrupt Task Group ************************* Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards. Provide both hardware specifications and software ABIs/APIs. Standardize compiler conventions for annotating interrupt handler functions.

Startup of the group that will work on managing additions to the Sail model and related output.

Unified I/O MMU specification covering the full range of Application-class systems ranging from Embedded to Cloud Servers. Community Google Drive folder at: https://drive.google.com/drive/folders/1LAKYRsDTAAzZE_e3RbRvmdo5y40CoVik Community GitHub at https://github.com/riscv-admin/iommu

The TG will propose the I/O Physical Memory Protection Unit ( IOPMP) as a hardware component on the bus fabric to prevent sensitive data leakage or temper via compromised I/O agents. IOPMP checks every access on the fly according to a set of predefined rules, each including the access issuer, the target address, and desired operations. The delivered (non-ISA) specification will cover as many scenarios and platforms as possible by providing various options.

********************** J Extension Task Group ********************** The RISC-V J extension aims to make RISC-V an attractive target for languages that are traditionally interpreted or JIT compiled, or which require large runtime libraries or language-level virtual machines. Examples include (but are not limited to) C#, Go, Haskell, Java, JavaScript, OCaml, PHP, Python, R, Ruby, Scala or WebAssembly. Among other topics, the group expects to collaborate with several existing RISC-V extension working groups.

*M-mode Isolation TG* The M-mode Isolation TG will develop one or more privileged ISA extensions to support isolation of M-mode software. For more details, see the Charter ( https://github.com/riscv-admin/m-mode-isolation/blob/main/CHARTER.md ).

********************** Nexus Trace Task Group ********************** The Nexus Trace Task Group is responsible for analysis of Nexus IEEE-ISTO 5001™ standard and it's applicability for trace of RISC-V cores. The Nexus standard is well established, silicon proven and extensively documented. It's necessary to define parts of the standard that are applicable to RISC-V trace. Github repo: *https://github.com/riscv/tg- nexus-trace ( https://github.com/riscv/tg-nexus-trace )* contains working documents and reference C code for encoder and decoder. * * The following parts of Nexus specification will be addressed: * Nexus compatible trace encoding * Trace control * Trace configuration * On-chip and off-chip trace routing * Physical trace connector options This group will not address the debug part of the Nexus standard. The group’s progress shall be evaluated after 4 months, at which time the charter may be revised if necessary to narrow the scope of effort. Chair: Robert Chyla Robert.Chyla@iar.com Vice-Chair: Neal Stollon Neal.Stollon@wdc.com

This TG will establish a specification for targeting Operating System and Kernels’ environment for booting and running those OSes on application class RISC-V machines. The specification will be used as a dependency basis for the OS-A Platform specification.

*************************** Software Overlay Task Group *************************** github: https://github.com/riscv/riscv-overlay *Motivation* In the early days of embedded computing there was a technique to load code in Real-Time at the moment it was needed for execution. Back then memory was expensive in all aspects. Similarly, today, IoT devices are very restricted with memory size and power. Due to those needs, the need for reviving the overlay concept, with RISC-V ISA, was needed along with RISC-V toolchain to support it. Charter The Software Overlay TG will specify the requirements for the software overlay feature, both from the FW manager engine and from toolchain aspects, all of which will be based on the current RISC-V ISA and extensions. *Deliverable* Full operation software stack to be part of RISC-V toolchain, includes runtime software and toolchain support. Initial Roadmap (by Phases) Gather * Gathering specification and requirements: what we wish this feature to contain * Making generic software requirements to be approved by the TG Design * Establish a software spec based on the requirements * Designing RT FW, using RISC-V ISA * Designing Toolchain usage * Write HLD (High-level design) for the RT engine Implementation * Implementation and LLD (low-level design) * Deployment * Write Test suite

********************** P Extension Task Group ********************** *Charter* : Define and ratify Packed-SIMD DSP extension instructions operating on XLEN-bit integer registers for embedded RISC-V processors. The TG will also define compiler intrinsic functions that can be directly used in high-level programming languages.

Explore and recommend RISC-V Instruction Set Architecture (ISA) Extensions that enhance performance and implementation efficiency for contemporary public-key cryptography, with a focus on standard Post-Quantum Cryptography algorithms like Kyber, Dilithium, and others. The ISA design and evaluation prioritize the requirements of real-world networked devices, ensuring that the Post-Quantum Cryptography (PQC) extensions effectively complement existing scalar and vector cryptography extensions.

********************************** Privileged Architecture Task Group ********************************** *Charter* : The Privileged Architecture Task Group's charter is to define and facilitate the ratification of a Privileged Architecture Specification suitable for embedded systems and Unix-like operating systems.

The Profiles working groups is a non-meeting group (all discussion via the mailing list) which works under the TSC's guidance to create the Profiles document.  The group leadership falls to the Unpriv and Priv IC chairs. All members may join and participate in the mailing list discussion.

The Platform Runtime Services(PRS) 2022 TG drives the standardization for various platform services required for interaction between the supervisor software and the firmware through ownership of the Supervisor Binary Interface(SBI), Advanced Configuration and Power Interface(ACPI), Unified Extensible Firmware Interface (UEFI) specifications.

psABI Task Group

The RERI (RAS Error-record Register Interface) TG will develop a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors and configuring means to report the error to handler component.

The RAS Terms & Definitions TG will establish a framework of terms and definitions for physical mechanisms starting from common ones from research and development to adapting the terms as needed. The terms and definitions will be applicable to RAS interactions to all application domains and system architectures of the RISC-V ecosystem.

RVM-CSI Version 1 Specification Task Group Note: the RVM-CSI specification work is being guided by the RVM-CSI SIG.  Please join it ( here ( https://lists.riscv.org/g/sig-rvm-csi ) ) to contribute, participate, or just follow the strategy and gaps discussions associated with RVM-CSI.

The RISC-V Vector C intrinsics TG will aim to work towards the v1.0.0 of the RISC-V Vector C intrinsics. The RISC-V Vector C intrinsics is the set of C intrinsic that allows programmers to leverage RISC-V Vector extension instructions in a high-level programming language like C.

The Technology HC is an umbrella HC that will provide strategy and oversight for technology sectors encompassing multiple industries and extensions in RISC-V ISA and ISA ecosystem (e.g. Embedded SIG under the HC will cover topics across industries like Automotive, Controllers, Wearables, etc. and groups like Code Size Reduction, EABI, etc.). Thi s HC will identify gaps across industries and RISC-V groups and create SIGs/TGs/HCs that will address these gaps. It will be a home for any SIGs/TGs/HCs that are created and represent them to the greater RVI community.  Sign off for other TG/HC work will flow through the Technology HC to the corresponding SIGs under it. The HC will also help the groups under its umbrella successfully interoperate and influence other groups regarding their topic areas. Finally, the HC will help its constituents' groups evolve to become a HC or TG as appropriate.

RISC-V is lacking documentation that provides security guidance for RISC-V designers and implementers. The Security Model TG will create a specification that outlines requirements and recommendations for RISC-V based platforms.

The RISC-V Server SoC specification TG shall use the GitHub repo and mail list to develop the RISC-V Server SoC specification.

The SPMP Task Group develops the SPMP (S-mode Physical Memory Protection) extension for memory isolation as an alternative to the paged virtual memory system. The Task Group will deliver an SPMP architectural specification and hardware/software PoCs.

The SS-LP-CFI task group will define privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow. Specifically, for protecting backward-edges we will define a shadow stack for storing return-addresses in each privilege level. For protecting forward-edges we will design a flexible label based landing pads approach which will ensure that the execution adheres to the application’s Control-Flow Graph. The design will follow the threat model compiled in CFI-SIG and will be updated on demand. Link to TG folder ( https://drive.google.com/drive/folders/1Bn2WjV1_K5gVveSFt3qSPktgCUpFWuBW ) Link to TG github ( https://github.com/riscv/riscv-cfi )

**************************************** Trusted Execution Environment Task Group ****************************************

UNIX-Class Platform Specification Task Group *Charter* : manage the UNIX-class platform specification. This working group will start by defining a subset of this platform specification that both allows compatibility with existing implementations and extensibility for the future needs

************************************ Unprivileged Architecture Task Group ************************************

The Microarchitecture Side-Channel Resistant Instruction Spans Task Group (uSCR-IS TG) is working to prevent timing covert channels in the RISC-V microarchitecture.

The V Extension Task Group is tasked with developing the specification for the RISC-V base V vector extension, including written documentation, executable model, and compliance suite.  The group is also responsible for outlining how future vector extensions can build on this baseline. Meetings are Fridays at 8am PDT. Please see the Google Calendar for technical groups. https://calendar.google.com/calendar/u/0/embed?src=c_sumcgd4h4k09ktuppmqjb27o1s@group.calendar.google.com&ctz=America/Los_Angeles

Technical Verticals Standing Committee

The Program Committee for Workshops is responsible for guiding the content and supporting/advising on the organization of  RISC-V Workshops.

The RISC-V Marketing Committee Chair: Ted Marena (Cadence Design Systems) RISC-V International Lead: Tiffany Sparks

Promote awareness, learning and adoption of the RISC-V ISA in the Asia Pacific Region.

RISC-V Marketing Committee Task Group Chairs & Vice Chairs

The RISC-V Marketing Content Committee Chair: Trina Watt (Imagination Technologies) RISC-V International Lead: Thea Clay, Anisha Sharma

The RISC-V Marketing Events Committee. Chair: Omar Hassen (Ventana Micro Systems) RISC-V International Lead: Tiffany Sparks

RISC-V Marketing Local Event Leads

Charter 1. Identify targeted market research on RISC-V which would be of interest to the RISC-V membership at large. 2. Facilitate and support research by 3rd party analyst firms on selected topics. 3. In conjunction with Racepoint and RISC-V International staff, liaise with market researchers and analysts who are preparing RISC-V related reports. (Note: At this time, it is anticipated that the targeted research will not be funded or sponsored by the foundation or by member sponsorships. Rather, the resulting reports will be offered for a fee by the research organizations).

RISC-V Board of Directors *RISC-V BOD Strategic Topics 2023* January 2023: Board engagement forums, RISC-V Organization Structure ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-01 ) February 2023: Legal discussion: Board only meetings, Board sub-committees update, high level strategy walk through ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-02 ) March 2023: Software directed fund “RISE” and ecosystem engagement, 2023 strategy, IPR Policy, Board delegates engagement on the board ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-03 ) April 2023: Board delegates engagement on Board and stronger Antitrust policy, 1Q Budget update, Developer Experience Board Update ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-04 ) May 2023: Compliance & Certification Update ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-05 ) June 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-06 ) July 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-07 ) August 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-08 ) September 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-09 ) October 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-10 ) November 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-11 ) December 2023: ( https://lists.riscv.org/g/bod/files/Meetings/2023/2023-12 ) RISC-V BOD Strategic Topics 2022 January 2022: Strategic Planning ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-01 ) February 2022: Legal Updates ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-02 ) March 2022: Software Ecosystem ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-03 ) April 2022: Contributor Culture ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-04 ) May 2022: Technical organization strategy ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-05 ) June 2022: Marketing plan overview, contributor culture ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-06 ) July 2022: IP Policy ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-07 ) August 2022: RISC-V Recognition program ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-08 ) September 2022: Update on Summit, Industry themes and focus for 2023 ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-09 ) October 2022: Nominations for Award, Summit update, Messaging update, LF Relationship ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-10 ) November 2022: Budget ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-11 ) December 2022: Technical Strategic topics: profiles, extensions, developer experience, marketing strategic topics: summit, messaging/positioning, positioning on IP FUD, Arm influence, events ( https://lists.riscv.org/g/bod/files/Meetings/2022/2022-12 ) RISC-V BOD Strategic Topics 2021 Jan 2021: Strategic topic brainstorming ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-01 ) Feb 2021: Technical leadership ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-02 ) Mar 2021: Summit planning & TSC composition ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-03 ) April 2021: Growth trajectory ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-04 ) May 2021: Extended technical conversation ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-05 ) June 2021: Mid-year Update ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-06 ) July 2021: Strategic topic brainstorming ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-07 ) Aug. 2021: Additional strategic topic brainstorming ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-08 ) Sept. 2021: ISA & Software Ecosystem ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-09 ) Oct. 2021: Automotive ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-10 ) Nov. 2021: Data Center / Cloud ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-11 ) Dec. 2021: Security ( https://lists.riscv.org/g/bod/files/Meetings/2021/2021-12 ) --------------------------------------------------------------------------------- RISC-V BOD Strategic Topics 2020 October 2020: Community engagement and shifting to a contributor culture (rather than "volunteer" dependency) ( https://lists.riscv.org/g/bod/files/Meetings/2020/2020-10 ) November 2020: How can we make the best progress on the most important topics for RISC-V? How many topics can we accelerate? ( https://lists.riscv.org/g/bod/files/Meetings/2020/2020-11 ) December 2020: Accelerating RISC-V beyond embedded and current domains into cloud, scale-out, PCs, AI, etc. including engagement of industry thought leaders ( https://lists.riscv.org/g/bod/files/Meetings/2020/2020-12 )

Building on the RISC-V Foundation’s growing footprint in China across more than 25 organizations and universities, the China Advisory Committee will guide the RISC-V Foundation’s education and adoption strategies to further accelerate the RISC-V ecosystem in the region. Participation in this committee is open to foundation members who have significant China-based operations.

********************************************* Special Interest Group: Academia and Training ********************************************* The Mission of the Academic and Training Special Interest Group is to promote RISC-V as a common platform based on an open ISA. The group supports educators and students with resources to further their education on all levels of the hardware and software stack, using the RISC-V ecosystem of solutions. The group's aim is to increase adoption of RISC-V to prepare computer and electronic engineers for the challenges and opportunities of the future. *Meetings: This group meets on the 2nd and 4th Thursday of the month at 8 AM Pacific.* Email reminders with agendas, meeting log in details and meeting minutes are distributed to the group. Note that this internal group also has a correspondence with the public group riscv-teach@groups.riscv.org ( https://groups.google.com/a/groups.riscv.org/forum/#!forum/riscv-teach ) for non-members. The repository for educational materials is public on the RISC-V Website ( https://riscv.org/learn/ ). It was previously listed on github ( https://github.com/riscvarchive/educational-materials ).

Android SIG under the Software Horizontal Committee The preliminary charter of the Android SIG is as follows: Scope： * Improve the functionality，efficiency，robustness of RISC-V supports on Android software stack. * Enabling RISC-V based Android device development and make RISC-V Android products a reality in the near future. * Liaise with Google and Android community to coordinate the upstream and maintenance affairs. * Arrange and coordinate efforts of developers from different entities willing to contribute to the implementation of AOSP on RISC-V. Goal: * Maintain a stable version AOSP on RISC-V repository for device development. * Maintain an up-to-date version AOSP on RISC-V repository for upstream patchwork. * Upstream the RISC-V supports patches to the AOSP projects, Linux kernel and external projects; and get them into the chunk. * Optimize the system overall performance to competitive level，and provides a fluent user experience. * Ensure the entire port is fully compatible with the Android Compatibility Definition Document (CDD) and can pass the Compatibility Test Suite (CTS). * Help developing and maintaining AOSP supports for 1~2 RISC-V evaluate boards (available from online shop). Chair: Mao Han han_mao@linux.alibaba.com Vice-Chair: Zheng Zhang Zheng.Zhang@imgtec.com

********************* Architecture Test SIG ********************* Define coverage requirements for RV32I compliance tests, release compliance test format spec, release compliance suite for RV32I For bugs & ongoing tasks in Jira, please see the Jira project for Compliance ( https://jira.riscv.org/projects/CSC/issues/CSC-1?filter=allopenissues )

The Automotive SIG provides a global forum for technical and strategic input into activities enabling or accelerating adoption of RISC-V related technology in the Automotive industry.

The CHERI SIG will work on a strategy for adding a capability based security model (CHERI) to the RISC-V ISA. Enabling a capability-based security model will ensure that RISC-V can provide strong security guarantees as well as mechanisms for compartmentalization that are more scalable than traditional MMU/PMP-based techniques. This SIG will work towards defining a CHERI-enabled instruction set, toolchain requirements, programming model and psABI.

Charter coming soon.

The Control Flow Integrity Special Interest Group (CFI SIG) will focus on c ode reuse attacks are based on diverting the control flow of an application by overwriting critical flow control variables. The SIG GitHub repo can be found at https://github.com/riscv-admin/control-flow-integrity/

Datacenter SIG Group https://github.com/riscv-admin/datacenter

Debug, Trace, and Performance Monitoring Special Interest Group (SIG) will c oordinate and prioritize debug, trace and performance monitoring activities for RISC-V.

Discussions, recommendations and improvements of the tooling and automations deployed to support the complete documentation landscape for the RISC-V project. This currently includes the Unprivileged ISA specification, Privileged ISA specification, a templated version of the extension specifications.

Embedded Special Interested Group

The Floating Point (FP) SIG will manage the existing FP formats and evaluate emerging formats for inclusion in the RISC-V architecture. When needed, the SIG will work with the Priv and Unpriv ISA Committees (ICs) to create task groups (TGs) to define the necessary ISA extensions.

This is the mailing list for the Graphics and ML Special Interest Group. You can find more details about our activities and roadmap on the GitHub repo ( https://github.com/riscv-admin/graphics ).

Special Interest Group: High-Performance Computing (HPC) This group is for discussions around HPC related to RISC-V

The Hypervisor Special Interest Group (SIG) is focused on coordinating progress across various open-source hypervisors, coordinating progress on their tools, discussing ideas for improving RISC-V support for hypervisors, and working with a variety of specifications to ensure robust virtualization solutions.

Japan Special Interest Group

Managed Runtimes SIG under the Software Horizontal Committee

The Performance Analysis SIG will ensure the development of leading edge end-to-end solutions for profiling and optimizing software running on RISC-V processors. Solutions include analysis ISA, profiling and analysis/visualization tools, and system software enabling.

The Performance Modeling SIG will work to address our community's need for cycle-accurate simulation and aims to establish a common workflow and toolscape to use through the product lifecycle (i.e. from design to analysis of hot loops in application development/compiler development).

The QEMU SIG aims to: * Coordinate with the upstream QEMU community and RISC-V contributors; * Identify gaps and maintain a status/roadmap for RISC-V support in QEMU; * Recruit reviewers and contributors to QEMU within the RISC-V ecosystem; * Provide guidance and training for other groups within RISC-V that contribute to QEMU (e.g., as part of the Acceptance Criteria for new extensions) and assist/coordinate the upstreaming of RISC-V specific contributions; The group will work closely with the Applications & Tools HC and coordinate with the other HCs and ICs to ensure that QEMU supports the ongoing standardisation efforts within RISC-V.

The Quality of Service (QoS) SIG will work to identify high-priority gaps relating to quality of service in the RISC-V ecosystem, and to define a strategy for achieving deterministic performance by minimizing the interference caused by contention for shared resources.

In order to promote development of RISC-V in server domain, we need a complete specification to guide implementation of RAS in the design of SoC, firmware and OS. Tasks in scope include: RAS terminology interpretation: Interpretation of RAS concept and terminology (e.g. diagnosability, recoverability, types of error). RAS framework design: A framework covers the full path of error handling: * Error recording: Standard error record formats (e.g. register banks, APEI­) * Error reporting: Error event reporting methods (e.g. exceptions, NMI, local/global interrupts) * Error recovery: strategies adopted to handle the error (e.g. neglect/warning/recover/isolation/halt) RAS feature support: Engage specific RAS features into the framework: * E2E Data protection * error isolation * data poisoning containment; * advanced error reporting for PCIe

Explore and propose security mechanisms related to runtime integrity that may be efficiently implemented at the ISA level, to provide strong security guarantees, and bridge the gap between RISC-V and other architectures.

The RVM-CSI SIG drives the strategy and coordinates the development of RISC-V’s Common Software Interface (CSI) for RISC-V Microcontrollers. Note: the RVM-CSI specification work is being done under the RVM-CSI Version 1 Specification Task group.  Please join it ( here ( https://lists.riscv.org/g/tech-rvm-csi-spec-v1 ) ) to contribute, participate, or just follow along.

The RISC-V Foundation Functional Safety Special Interest Group

The Special Interest Group (SIG) focused on Simulators

Soft CPU Special Interest Group

Toolchain Special Interest Group (SIG) Mailing list for the RISC-V toolchain efforts.

There is a growing need for a Zero-Trust architecture in HW, where a software application can both examine and attest to the environment it is running in, and have guarantees that it is isolated from other, untrusted software. The Trusted Computing SIG will examine the state of the art for hardware-assisted technologies such as Confidential Computing, Remote Attestation, Confidential VM, Hardware TEE, Enclaves, etc., on an ongoing basis,  and define the trusted computing strategy for RISC-V. It will develop TG Charters as required, that will define the required written documentation, threat models, executable model, prototype implementations including SW PoCs, toolchain support, and compliance suite for RISC-V trusted execution recommendations and extensions. Shared Folder for meetings: link ( https://drive.google.com/drive/folders/1N_W73Nh-uNvmlcYsdiUWPK0wktXKGSlO ) Github (largely archival): link ( https://github.com/riscv-admin/trusted-computing )

The Microarchitecture Side Channels Special Interest Group (uSC SIG) focuses on the RISC-V strategy to prevent microarchitectural information leakage, with an initial focus on timing side channels. The GitHub repo for the community is at https://github.com/riscv-admin/uarch-side-channels.

The Vector SIG will serve as the group responsible for considering all vector extensions to the RISC-V ISA in the future. They will evaluate new proposals, create their own if needed, and work to create task groups (TGs) for new extensions as needed.

Blockchain SIG is proposed to develop a strategy and provide oversight for blockchain technology and solutions in RISC-V architecture and software ecosystem.  the goals are to ensure there are no gaps in the ISA or software and it meets or exceeds industry expectation in performance and security (e.g. privacy-preserving, cryptographic algorithms, Trusted Execution, data ownership, integrity, provenance, etc.) In addition, the Blockchain SIG will work with the Implementation HC to make sure someone in the community develops a RISC-V based Proof of Concept (PoC) to ensure the whole stack from HW to SW meets the goals. As with all groups, the SIG will engage and interact with other appropriate committees and groups.

Continuous Integration & Testing

************************************************************************************************************************************** ***** [Suspended]. Please join the Trusted Computing SIG ( https://lists.riscv.org/g/sig-trusted-computing ) ****** ************************************************************************************************************************************* Security SIG is focused on hardware-assisted technologies such as Control Flow Integrity, Secure Boot, Root of Trust, Side Channel Mitigations, Software Compartmentalization, etc., and other future promising topics for RISC-V.

******************* BitManip Task Group ******************* The BitManip work group will define extensions to the Unprivileged ISA that are comprised of bit-based instructions. These extensions are intended to enable the development of code that is substantially more performant and efficient that what is possible with the base instructions. Performance testing will be conducted by compiling or hand-assembling routines and then measuring performance improvement in a RISC-V modelling environment. Where possible, all or portions of standard benchmark tests will be employed in this testing. The new instructions will include operations from one or more of the following categories: bit counts, shift/rotate, insert/extract, set/clear, permute, and logical/mask. A base extension will include commonly used functions that are simpler to implement. An extended extension will be proposed should there be instructions that provide even more performance and power savings at a cost of more complexity.

Cache Management Operations Task Group Note: The RISC-V CMO TG is currently in maintenance mode. Updates to the existing extensions, Zicbom, Zicboz, and Zicbop, will be made as necessary. Please contact help@riscv.org with any questions.

EABI Task Group Chair: Michael Yu (Huawei) Vice-Chair: Cooper Qu (Alibaba) Charter The EABI Task Group is to define a new ABI for RISC-V embedded systems, including Calling convention, C type details and ELF Object Files . The new ABI is intended for embedded targets only, designed to reduce the interrupt latency with a balanced performance and codesize, and work same on all RISC-V embedded targets with same XLEN. Deliverables 1. A complete specification of EABI. Roadmap 1.  Specify the benchmarks to measure the code size and performance. 2.  Specify the Calling Convention, including integer register and floating point register. 3.  Specify C type details and ELF Object Files.

******************************* Formal Specification Task Group ******************************* This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness. It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers.  It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs. [ This work is closely related to and complementary to the work of the  Memory Model Task Group ]

*********************** Memory Model Task Group *********************** The memory model task group charter is to define the memory consistency model for the RISC-V architecture, to produce relevant documentation and supplementary material (such as formal mathematical specifications and compliance test cases), and to work with the other task groups to ensure their own specifications remain compatible with the memory model.

1) establish performance regression tests (and who and how we run them as a community minimizing duplication) over a broad set of benchmarks to recognize any issue we introduce by virtue of new instructions or tool chain changes both before and after ratification 2) identify benchmarks to verify the effectiveness of extensions and the tool chain changes to exploit them to see if they meet the goals set out in the change rationale before ratification 3) provide a group to discuss and share non proprietary implementation of products and ecosystem pieces to make RISC-V competitive and innovative including optimizers 4) identify further ISA extensions that could help benchmark performance and therefore RISC-V based products 5) Worst Case Execution Time (WCET) (functional safety) 6) Spatial & Timing interference (functional safety)

Virtual Memory Task Group ------------------------- Chair: Daniel Lustig Vice Chair: Andrea Mondelli Charter The goal of the Virtual Memory Task Group is to improve RISC-V support for large scale virtual memory systems.  Tasks in scope include: adding a page table format supporting 64KiB pages and larger address spaces, filling in gaps in the specification of TLB synchronization, and adding a PMA/PMP alternative that encodes coherence/cache-ability by virtual address rather than physical address.

Charter The Zfinx task group will specify how to share the integer (X) registers with the floating point (F) registers, to save silicon area and to free up encoding space. The group will specify the requirements for the ISA and the toolchain. The charter covers RV32 and RV64 implementations with D (64-bit), F (32-bit) and Zfh (16-bit) floating point registers. RV128 and Q(128-bit) are considered out of scope, but should be resolvable as a simple extension to the final specification. Deliverables 1.  A complete specification of Zfinx for inclusion in the RISC-V ISA manual Roadmap 1.  Completely specify RV32F Zfinx, RV32FD Zfinx 2.  Extend to RV32D where XLEN < FLEN 3.  Deliver SAIL model, QEMU model 4.  Pass architectural tests 5.  Delivery of GCC and GDB

************************ RISC-V All-Members Group ************************ Welcome to the RISC-V Members group server! The subgroups here are moderated, members-only discussions related to the development of the RISC-V ISA. The primary website for the RISC-V architecture is at https://riscv.org. To become a member of the RISC-V International community, please see https://riscv.org/membership-application The groups on this server are currently restricted to members who have signed the membership agreement. There is also a set of public mailing lists that does not require membership - you can join these discussions here: https://groups.google.com/a/groups.riscv.org This server provides discussion lists, calendars, and other services for RISC-V members, including: * technical working groups (tech-*) * marketing working groups (mktg-*) * special interest discussion groups (sig-*) * administrative groups This group " allmem " is for announcements to all members, and posting is restricted to RISC-V International Staff. Traffic on this list is extremely low. Discussions take place in other groups - you can view and join these subgroups by clicking "Subgroups" on the left side of this screen. Within each group, after joining the group, you can view Messages , Calendar , Files , and Wiki using the links on the left side. You can return to the main group by clicking " Your groups " at the top and choosing " RISC-V main group ", and you can view server-wide information by clicking the RISCV text at the very top left of the screen. You can subscribe to each group's calendar individually, but most people find it easier to subscribe to all of your subgroup calendars at once. Click RISCV and then Your Calendar to view or subscribe to a compilation of all of the calendars for the subgroups to which you are subscribed. To subscribe, scroll to the bottom of a calendar page, click " Subscribe to Calendar ", make a copy of the iCalendar URL and subscribe (not import) using your calendar software. Note that some users of Outlook have described time zone issues with iCalendar links, so please double-check meeting times. Finally, for every group, you can choose whether your profile is visible to others. By default, your profile is not visible. To make it visible, click your name in the upper right corner and choose " My Account ", then click the Identity tab. You can customize your profile for each group you are subscribed to. Changes made to your account profile will automatically apply to each group profile, with the exception of those specific fields in each group profile that you've previously customized.

RISC-V Lab Partners will be developing CI/CD labs and sandboxes.