On behalf of the Architecture Review Committee (ARC) and John Hauser (the lead architect and author of the AIA spec): Before the AIA is ratified, the ARC has recently identified a mistake in the AIA s

AIA experts, In reading the AIA specification, it's seen that mtopi and stopi both have an IPRIO field which gets its value from the iprio array for its associated privilege level. One permitted imple

Hello AIA experts, For CSR hvictl, the AIA spec subtly suggests (but does not explicitly state) that all 8 bits of the IPRIO field must be implemented as read/write bits. For the simplified case where

@tech-aia, Anup Patel, and John Hauser, could you help with some pointers here? (I could not find a reference to it in the GH Repo nor in the mailing list history). -- Obrigado | Thank You Rafael Peri

Greetings! We are delighted to announce the start of the public review period for the following specifications: 1. RISC-V Input-Output Memory Management Unit (IOMMU) specification 2. Advanced Interrup

Hello, AIA TG, As you may know, the AIA completed official public review last month without incident, putting it much closer to ratification now. However, back in November, just before public review b

Hi All, The public review of the AIA specification was completed on 24th Dec 2022. Next, we proceed towards final ratification. I am cancelling the regular AIA meeting series to free-up the time slot

Hi, I see that APLIC has ithreshold control but I don't see anything similar for the AIA local interrupts (Interrupts for Machine and Supervisor Levels chapter). Is that correct? It seems like a usefu

Hi all, There were concerns about the draft chapters of the frozen AIA spec. In particular, there is the risk of changes to the ratified chapters of the AIA spec once the draft chapters will advance.

Hi All, The public review of AIA specification is in-progress until 24-12-2022 (inclusive) so cancelling the next AIA meeting on 08-11-2022 due to lack of topics to discuss. If there are any open issu

Hi All, The AIA specification is frozen and already in public review so cancelling the next AIA meeting on 10-11-2022 due to lack of topics to discuss. If there are any open issues/topics to be discus

To all interested in the AIA, A couple of small but significant errors have been discovered in the draft AIA concerning VS-level interrupts. First up, I realized I made some mistakes in the list of in

Hi guys, The more I think about it, the more I realize I made a mistake in the AIA concerning an IOMMU's MSI page tables. The current draft says they apply only to naturally aligned 32-bit writes, but

I would like to ask for a bit of clarification regarding the xtopi CSRs (mtopi, stopi, vstopi). The definition of each register indicates bits 27:16 are IID, interrupt ID, which is the highest priorit

Hi All, The next AIA meeting on 13-10-2022 is cancelled due to lack of topics to discuss. Currently, we are on track for the freeze and public review of the AIA specification by Dec 2022. If there are

I am finding it challenging to understand the intent, meaning, and interpretation of Tables 6.3 and 6.5 in the AIA specification. It appears to be trying to communicate the effect of changing the ipri

My understanding is that setting domaincfg.IE to 0 should only affect whether interrupts are delivered from the APLIC to the attached harts. In particular, when domaincfg.IE=0, reading setip will stil

Hi All, The next AIA meeting on 08-09-2022 is cancelled due to lack of topics to discuss. If there are any open issues/topics to be discussed then we can have an ad-hoc meeting for the same. Regards,

Hi All, Last month (Aug 2022), the latest AIA draft spec (v0.3.1) was approved by the Arch Review (AR) committee so the AIA specification is officially in stable state. (Refer, https://github.com/risc

Hi, The current AIA spec refers to "standard local interrupts" in Section 6.4 Interrupts at supervisor level: "If a standard local interrupt becomes pending (= 1) in sip/siph, the bit in sip/siph is w