We are pleased to confirm Dr. Xichuan Zhou, of Chongqing University, to the role as the Chair of the AI/ML task group at RISC-V.  Additionally, Suresh Sugumar, currently the Executive Director for RISC-V Research at Technology Innovation Institute (TII), will assume the role of the Vice-Chair.

Their respective biographies are:

• Dr. Xichuan Zhou received the B.S. and Ph.D. degrees from Zhejiang University, Hangzhou, China, in 2005 and 2010, respectively. He was a visiting scholar to Arizona State University in 2009. He is currently a professor and the director of the Institute of Science on Brain Inspired Intelligence in Chongqing University (http://isbi.cqu.edu.cn/) in China. Now he is the acting chair of the Artificial Intelligence & Machine Learning SIG. He is also the TPC Member of the AAAI (2019-2022) and many other academic conferences, and executive member of multiple Chinese Computer Federation Expert Committees.
  Professor Zhou made original contributions in intelligent edge computing, significantly contributing to both efficient deep learning methods and engineering applications. He is leading a dozen research projects now, and the total funding of his team is over fifty million RMB for the last a few years. He has authored or co-authored over 70 papers in prestigious international journals and conferences, including IEEE TCAS-1, TNNLS, TED, TBME,  GRSL,  SPL and ICML, AAAI, CVPR. His book of Deep Learning on Edge Computing Devices is one of the earliest books covering multidisciplinary topics from algorithm to hardware design of embedded AI systems. He also held over a dozen patents, and has given dozens of keynote speeches and invited talks, chaired several conferences. He was awarded the Outstanding Scientist of Chinese Institute of Electronics in 2021.
• Suresh Sugumar's research focuses on developing autonomous and secure RISC-V based systems. He leads a team to build open-source RISC-V SoC and collaborates with university partners in advancing Security/ AI accelerator research. He actively contributes to RISC-V advancements where he chairs Trusted Computing SIG that defines and creates specifications for Confidential Computing, and also is co-authoring the RISC-V Platform Security Model. Suresh is a Senior Member of IEEE, holds 15+ patents, and published several articles and research papers in international conferences. He had worked at Intel, Qualcomm, and MediaTek for ~20 years in various leadership roles. Suresh is currently an Executive Director for RISC-V Research at Technology Innovation Institute (TII) based in Abu Dhabi. He earned his MBA from INSEAD Singapore, and an MS from the Birla Institute of Technology & Science, India.

The appointments of Xichuan and Suresh—they had already stepped up as acting chairs for the reformed group—will bring a wealth of expertise to the task group. We anticipate significant progress and developments under their leadership.

As we discussed in last week's Applications & Tools HC meeting, we are also exploring the formation of a sibling SIG to focus on the AI/ML software and compiler aspects.  This step will free up the existing AI/ML SIG to focus on architectural gaps for AI/ML and on emerging techniques for AI/ML.

Please join me in welcoming them to their new roles,
Philipp Tomsich
Chair, Applications & Tools Software HC