Confirming Iain Robertson and Paul Donahue as chairs of DTPM SIG

Ved Shanbhogue

Greetings !

We are pleased to announce that the SoC infrastructure HC in accordance with Groups & Elections Policy has approved the preliminary charter for the Debug, Trace, and Performance Monitoring (DTPM) SIG.

They have also approved Iain Robertson from company Siemens as the chair and Paul Donahue from company Ventana Micro Systems as the vice-chair.

Their respective bios are:

  • Iain Robertson - has over 35 years experience in silicon design, architecture and engineering team leadership. Iain is an expert in monitoring, analytics, processor trace and debug, with past experience with SerDes design, memory subsystems, networking, DfT and transistor level circuits.  Iain holds over 50 patents in these areas.   Iain is currently Senior Hardware Engineering Director for Tessent Embedded Analytics, part of Siemens EDA, and was formerly VP Engineering at UltraSoC Technologies, which Siemens acquired in 2020.  Prior to joining UltraSoC in 2012, Iain worked at Texas Instruments on the company’s graphics processors, DSPs, Ethernet switches, SerDes devices and more. Iain holds a BSc (honors) in Physics from Imperial College, London.

  • Paul Donahue - After joining Ventana 4 years ago, Paul became active in the ETrace Task Group as it developed the first RISC-V instruction trace format.  Paul also became active in the Debug Task Group, stepping into the role of vice-chair for the last 2 years.  Paul has almost 30 years of CPU experience on a number of ISAs including 7 years of deep experience with the ARM debug and PMU architectures and exposure to ARM ETM.  He has written a bespoke external debugger for silicon debug of a CPU.

We want to acknowledge and thank Iain Robertson and Niranjan Prabhu for performing the role of acting chairs and getting us through the approval process and starting the DTPM SIG meetings.

We encourage you to participate in the DTPM SIG. Please “Join This Group” by clicking the blue button on the bottom of the community page.  You will find the group meetings and all RISC-V Technical Meetings on the RISC-V Technical Meeting calendar.  For more details on how to subscribe to the calendar, see the “Subscribing to the Technical Meetings Calendar” topic of the RISC-V Calendars, Meetings, and Zoom wiki page.

Please join me in congratulating the chair, vice-chair and the group Let’s all do our part to help make them successful.

Ved Shanbhogue and Gajinder Paneswar
SoC infrastructure HC chair and vice-chair