RISC-V ICE-V DevBoard Program Announce

Jeff Scheel

The RISC-V DevBoards Program would like to extend the project solicitation phase for the ICE-V board from QWERTY Embedded Design until February 28, 2023.  

This developer board can be thought of as a combination of an ESP32 SOC and a small FPGA and has the following details:
  • 82 mm x 32 mm board
  • ESP32C3HN4 SOC
  • 400 KB SRAM
  • 384 KB ROM
  • Lattice iCE40 FPGA (5k LUTs)
  • Wifi
  • Bluetooth
  • 1- USB
  • GPIO for serial
  • ADC
  • I2C
These compact boards should be well suited for educational and prototyping activities.  If you have a project, please apply by February 28, 2023 at the form found on the RISC-V Developer Boards "Details" page at:

Quantities are limited and projects will be evaluated on impact and timing of submission.

Please send questions to devboard-seed@....


Jeff Scheel (he/him/his)
Linux Foundation, RISC-V Technical Program Manager