Greetings ! We are pleased to announce that the SoC infrastructure HC in accordance with Groups & Elections Policy has approved the preliminary charter for the Debug, Trace, and Performance Monitoring

Colleagues, I am pleased to confirm Chris Owen and Vincent Cui for the roles of chair and vice-chair, respectively, of the RVM-CSI SIG. Both Chris and Vincent had already been Acting Chairs for the gr

Hi all, As per the policy governing chairs and vice chairs, we are holding a call for candidates for the positions of Chair and Vice-Chair for the RVM-CSI (RISC-V eMbedded – Common Software Interface)

This is a call for chair and vice-chair candidates for the recently created Debug Trace and Performance Monitoring (DTPM) SIG All candidates must submit a biography (bio) and statements of intent by 1

RISC-V Strategic Members, Last Fall, we were elected to represent you on the RISC-V Technical Steering Committee (TSC) in 2023. We are sending this message to you for two reasons: We will of course tr

We are delighted to announce the start of the public review period for the proposed Fast-Track extension Zihintntl to the RISC-V ISA. This extension adds non-temporal locality hints, which affect the

This is a call for chair and vice-chair candidates for the recently created Control Transfer History TG (umbrella: Perf Analysis SIG) All candidates must submit a biography (bio) and statements of int

Hi everyone, Here is the link for the recording and the presentation from our last RISC-V Technical Sessions presented by Robert Chyla and entitled N-Trace for RISC-V explained. Consider presenting in

The RISC-V DevBoards Program would like to extend the project solicitation phase for the ICE-V board from QWERTY Embedded Design until February 28, 2023. This developer board can be thought of as a co

This is a new call for chair and vice-chair candidates for the Vector SIG. All candidates must submit a biography (bio) and statements of intent by Feb 15, 2023. The current draft charter of the Vecto

Concluding discussions that go back to last year's Linux Plumbers Conference, I can finally announce the formation of a QEMU SIG under the governance of the RISC-V Applications & Tools HC. This group

We are pleased to confirm Dr. Xichuan Zhou, of Chongqing University, to the role as the Chair of the AI/ML task group at RISC-V. Additionally, Suresh Sugumar, currently the Executive Director for RISC

I am pleased to announce the selection of Ian Rogers as the new vice-chair of the Managed Runtimes SIG. Ian is a Staff Software Engineer at Google, where he is the tech lead for the ART runtime. His p

Hi all, I am delighted to announce that here at 10xEngineers (which is a partner of riscv-labs subgroup), we have launched an online CI platform called Cloud-V for testing RISC-V applications. Develop

Hello, Join us on February 2nd, 7 am Pacific Time to learn more about N-Trace for RISC-V. N-Trace (Nexus IEEE 5001 based trace) is approaching ratification and will provide yet another tool to advance

We are delighted to announce the start of the public review period for the following proposed standard extensions to the RISC-V ISA: Zvfh Zvfhmin The review period begins today, January 24, 2023 and e

I am pleased to announce the confirmation by the TSC of Paul Elliott as the new chair of the security model task group. I am sure you will join me in officially welcoming Paul to the role and that we

We are just a few days away from RISC-V Summit and there is still time to join some of the brightest minds in the RISC-V world, virtually or in-person. Don’t miss out on the action. In the last year b

I am pleased to announce the selection of Ravi Sahita of Rivos Inc., <ravi@...> as the new vice chair of the security horizontal committee. I am sure you will join me in welcoming Ravi to the role and

All, We are pleased to announce that the Unprivileged Spec IC in accordance with Groups & Elections Policy has approved the preliminary charter for the Floating Point SIG. They have also approved Kenn