Hi All, We are compiling a list of software projects that we'd like to report out on at the RISC-V summit. We have created a spreadsheet and noted specifics on their engagement with the RISC-V archite

All, The Performance Analysis SIG is pleased to announce the formation of the Control Transfer History TG, with Acting Chair Beeman Strong from Rivos, and Acting Vice Chair Bruce Ableidinger from SiFi

Hi all, This is a call for chair and vice-chair candidates for the recently created “RISC-V Vector C Intrinsics TG”. All candidates must submit a biography (bio) and statements of intent by November 2

This is a call for candidates for the position(s) of CHAIR & VICE-CHAIR for the AI/ML SIG. To nominate yourself or another community member, please send an email to help@... and include a short biogra

We are delighted to announce the start of the public review period for the RISC-V Advanced Interrupt Architecture (AIA) specification, which contains both ISA and non-ISA components. The RISC-V AIA sp

Looks like that link is broken, I'm assuming it's just missing the "f"? In the PDF I get when adding an "f", the preface there still says "Counters" as a draft at 2.0. The specification status wiki li

This is a call for candidates for the position of CHAIR / VICE-CHAIR for the Security Model TG, as the previous Chair Manuel Offenberg stepped down. To nominate yourself or another community member, p

We are delighted to announce the start of the public review period for the following proposed standard extensions to the RISC-V ISA: Zicntr - the standard extension for base counters and timers Zihpm

The old community has been resurrected (unarchived) and can be found at: sig-ai-ml@.... Please join Xichuan and Suresh there. -Jeff --Jeff Scheel (he/him/his) Linux Foundation, RISC-V Technical Progra

Dear colleagues, I am happy to confirm that—after a year of having our AI/ML SIG under the interim stewardship of the Graphics SIG leadership—we have concluded our search for Chairs and worked with th

All, I’d like to start by thanking our TSC reps for the past year: Ben Marshall, Gajinder Panesar, and Karel Masařík. Your insight at the CCM has been much appreciated as well as on the mailing list.

All, The Applications & Tools HC is pleased to announce the inception of the RISC-V Vector C intrinsics API TG with Acting Chair Eop Chen from SiFive. Note that a TG at inception has not received appr

All, we would like to announce that Peter Lewin (IMGTEC) has been named the chair of the newly formed Automotive SIG. We would like to thank Peter for his ongoing service to the RISC-V community! The

We are delighted to announce the start of the public review period for the RISC-V Profiles RVI20, RVA20, RVA22. The 45-day review period begins today, October 25, and ends on December 9 (inclusive). T

Hi All, Apologies on the typo here. We approved Andy's message after several days of discussion, so the call for candidates will end on Oct 27 (inclusive). Sorry for any confusion here. If you’re look

All, We are pleased to announce that the TSC in accordance with Groups & Elections Policy has approved the preliminary charter for the RAS terms and definitions TG under SoC Infra. HC. They have also

All, We are pleased to announce that the TSC in accordance with Groups & Elections Policy has approved the preliminary charter for the Cache and Memory Controller QoS Register Interface (CMQRI) TG und

It is with regret that I have to announce the stepping down of Manuel Offenberg as vice-chair of the Security Horizontal Committee. Due to a role change in his organisation he is unable to continue in

RISC-V Strategic, Community Org, and Individual Members, We are holding our yearly elections for the "Technical Steering Committee Representatives". We will elect 2 representatives from the Strategic

These RISC-V vector extensions to handle IEEE FP16 were defined prior to ratification of the vector specification, but were left out of RVV 1.0 as they were not to be included in the base V extension.