[riscv-CMOs:master] reported: How to discover the information of cache block size by software? #github #risv #CMOs

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software?
By ubc-guy:

in the vector spec, software needs to know the maximum length of a vector that can be used when stripmining. this varies greatly (more than cache line size) among implementations. hence, the 'setvl' instruction accepts an 'application vector length' as a request, and returns a value in 'rd' which saturates to the largest vector length the underlying implementation can support.

the cbo.* and prefetch.* instructions can potentially be modified to do this, since they presently force the 'rd' field as all zeros, but it would be a huge waste of opcode encoding space.

the other option is to implement a new instruction that returns the cache line size. i'm a bit surprised this was left out of the final spec, since it was talked about at one point. any such instruction would have to return the smallest line size used when there are multi-level caches.

adding a cache line size instruction might be possible via the fast track process. https://riscv.org/announcements/2021/02/risc-v-international-unveils-fast-track-architecture-extension-process-and-ratifies-zihintpause-extension/

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