[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By brucehoult: My understanding of the intent of the RVA ISA Profiles is that Linux distro

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <dkruckemyer@...>: 8e8a8e01e1e2: Create cmobase-v1.0.1.pdf Added: specifications/cmobase-v1.0.1.pdf [riscv-CMOs:master] New Comment o

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By brucehoult: I don't know if we have our own document specifying wordings such as this. I think most groups follow

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By dkruckemyer-ventana: I have the updates in a local repo, so no need to make any ch

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By dkruckemyer-ventana: As I'm thinking about this some more, it's not clear what req

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By AndyGlew: This may be long past caring for y'all, but at one point ( as in, origin

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[riscv-CMOs:master] New Comment on Pull Request #49 New textual form By dkruckemyer-ventana: There was some discussion on #47 that I'll add in. Next week. (And this time I mean it.... :) )

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By yulong-plct: How can I implement the textual format of cbo.* asm operands in the g

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By dkruckemyer-ventana: Just wanted to let everyone know I haven't forgotten about th

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By palmer-dabbelt: Looks like some support for these landed in binutils as 41d6ac5da6

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By a4lg: @dkruckemyer-ventana TL;DR: offset(rs1) looks good (for other reason than yo

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <47680170+dkruckemyer-ventana@...>: 7bfa11334dca: Update README.md Modified: README.md

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By dkruckemyer-ventana: @a4lg I have no problem with the change, though I wonder whet

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[riscv-CMOs:master] New Comment on Issue #50 Should exception be raised if the memory attribute is strong order for cbo.zero? By gfavor: Cbo.zero, as a form or memory-accessing instruction, is subject

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[riscv-CMOs:master] New Issue Created by xian-zju: #50 Should exception be raised if the memory attribute is strong order for cbo.zero? As defined by the spec in Chapter 4.2, cbo.zero is used for a ca

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[riscv/riscv-CMOs] Pull request updated by a4lg: #49 Alternative textual form This pull request implements new textual form as proposed by @asb. Here's some backgrounds (see #47): Alex Bradbury (@asb)

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By a4lg: Both (GNU/LLVM) toolchain developers agreed. Remaining task: ask RISC-V CMO

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[riscv/riscv-CMOs] Pull request opened by a4lg: #49 Alternative textual form This pull request implements new textual form as proposed by @asb (see #47).

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By jrtc27: Because offset must be zero, we cannot handle cbo.* instruction just like

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By cmuellner: There are two Binutils patches from January on the Binutils list, that

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