[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By aswaterman: I’ll support @jrtc27’s take. It’s [riscv-CMOs:master] New Comment on I

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By gfavor: The new (in development) "RISC-V unified low-level discovery method" will suppo

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[riscv-CMOs:master] New Issue Created by Jamesykm-andes: #48 How to discover the information of cache block size by software? In 2.7. Software Discovery section, some information needs to be discovere

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[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By jrtc27: Arguably, sfence.vma operates on the reference (which can affect the data

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[riscv-CMOs:master] New Issue Created by asb: #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' I'm about to post patches to enable MC layer support for Zicbo{m,z,p} in LLVM. O

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[riscv-CMOs:master] New Issue Created by asb: #47 Textual format for cbo.* asm operands - '(rs1')/'0(rs1)' vs 'rs1' I'm about to post patches to enable MC layer support for Zicbo{m,z,p} in LLVM. One p

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <dkruckemyer@...>: 3dd606fe92ce: Create cmobase-v1.0.pdf Added: specifications/cmobase-v1.0.pdf

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2 New Commits: [riscv-CMOs:master] By David Kruckemyer <dkruckemyer@...>: e7d0ce762a11: finalize cmobase update version in makefiles change state to ratified update colophon relax permiss

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[riscv/riscv-CMOs] Pull request opened by dkruckemyer-ventana: #46 finalize cmobase update version in makefiles change state to ratified update colophon relax permissions for mgmt CBOs

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[riscv-CMOs:master] New Comment on Issue #41 CBO instruction behavior when cache is disabled or when memory attribute is uncacheable By dkruckemyer-ventana: Closing since I believe the issue has been

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[riscv-CMOs:master] New Comment on Issue #45 Interaction between management instructions and dirty bit By jrtc27: Why wouldn't the driver do the invalidate then in that situation? It knows best whethe

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The CBIE bits in the menvcfg, senvcfg, and henvcfg registers provide exactly this functionality. Cheers, David

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[riscv-CMOs:master] New Comment on Issue #45 Interaction between management instructions and dirty bit By jrtc27: So, whilst in practice there may not be a security justification for mandating PTEs be

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[riscv-CMOs:master] New Issue Created by jrtc27: #45 Interaction between management instructions and dirty bit The prefetch and zeroing instructions are very clear about how they interact with the acc

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[riscv-CMOs:master] New Comment on Issue #44 Feedback on the 1.0-rc2 specification By dkruckemyer-ventana: Thanks for your feedback. I have some short responses and some longer responses, and unfortun

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[riscv-CMOs:master] New Issue Created by azuepke: #44 Feedback on the 1.0-rc2 specification Dear authors, here's some feedback to the 1.0-rc2 specification from a microkernel developer's point of view

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <dkruckemyer@...>: fc8e97a9531a: Create cmobase-v1.0-rc2.pdf Added: specifications/cmobase-v1.0-rc2.pdf

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[riscv/riscv-CMOs] Pull request opened by dkruckemyer-ventana: #43 Clarify order and access bits Clean up ambiguity around ordering instructions (besides FENCE) and accessed/dirty bits [riscv/riscv-CM

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <dkruckemyer@...>: e38836364259: Publish cmobase-v1.0-rc1 Added: specifications/cmobase-v1.0-rc1.pdf Removed: cmobase-v1.0-rc1.pdf

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[riscv/riscv-CMOs] Pull request closed by dkruckemyer-ventana: #42 Public review feedback Notes from the public review period: Feedback on sections 2.5.2 (Page Fault and Guest-Page Fault Exceptions) a

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