[riscv/riscv-CMOs] Pull request updated by dkruckemyer-ventana: #21 Add draft Zicmobase spec Created specifications folder and first draft of Zicmobase specification. See forthcoming email on mailing

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[riscv-CMOs:master] New Comment on Pull Request #21 Add draft Zicmobase spec By dkruckemyer-ventana: I can merge it, but I thought that inline commentary could only be added to a PR. I wanted to give

#github #risv #CMOs

[riscv/riscv-CMOs] Pull request opened by dkruckemyer-ventana: #21 Add draft Zicmobase spec Created specifications folder and first draft of Zicmobase specification. See forthcoming email on mailing l

#github #risv #CMOs

1 New Commit: [riscv-CMOs:master] By David Kruckemyer <47680170+dkruckemyer-ventana@...>: 312ba8e802f4: Update charter Removed "proposed" in title Changed "maintenance" to "manage

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[riscv-CMOs:master] New Comment on Issue #20 Does CBO.ZERO.EA need to be atomic? By dkruckemyer-ventana: RESOLVED: We will define CBO.ZERO.EA to be byte-atomic only. As guidance to software writers, w

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <47680170+dkruckemyer-ventana@...>: 8b99fd565f1a: Create CMO-Phase-1-Scope.md Added: CMO-Phase-1-Scope.md

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you either have CMO isa architectural rqmts or you dont. Its the atomic block a cache line? anything less is fatal. making some lower cost implementers trap and emulate software work should not be you

#github #risv #CMOs

[riscv-CMOs:master] New Comment on Issue #20 Does CBO.ZERO.EA need to be atomic? By ingallsj: Even with a lock, could CBO.ZERO.EA be trap-and-emulated atomically by executing the existing store instru

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They are clearly equivalent in this case, but I don't see why you would want to use DISCARD. I would vote for FLUSH.I or sooemthing.

#github #risv #CMOs

No, not a variant of discard. Discard says to mark a line clean and invalid, without writing dirty data back It is also cannot be a noop or a hint; it's effectively a shortcut for writing zeroes into

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1 New Commit: [riscv-CMOs:master] By AndyGlew <10249637+AndyGlew@...>: 7974cb713ea7: Update 2020-11-23_CMOs-TG--minutes--surrender.mediawiki Modified: agendas-and-minutes/2020-11-

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1 New Commit: [riscv-CMOs:master] By AndyGlew <10249637+AndyGlew@...>: d03c01ef7d84: Update and rename 2020-11-23_CMOs-TG-surrender-agenda to 2020-11-23_CMOs-TG-surrender-agenda.m

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1 New Commit: [riscv-CMOs:master] By AndyGlew <10249637+AndyGlew@...>: 862d1c4a5021: Update and rename 2020-11-23_CMOs-TG-surrender to 2020-11-23_CMOs-TG-surrender-agenda Formatte

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[riscv-CMOs:master] New Comment on Issue #15 Use cases for CMOs - collect By AndyGlew: Agreed: CMOS must ignore the cacheability attributes. That;'s not what I was talking about/ PTE.WB --> PTE.UC Bre

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1 New Commit: [riscv-CMOs:master] By AndyGlew <10249637+AndyGlew@...>: 8e3291859b6e: Update README.md riscv-CMOs/README.md points to riscv-CMOs discuss, but there is still *loads*

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1 New Commit: [riscv-CMOs:master] By AndyGlew <10249637+AndyGlew@...>: 8a186b45708c: Update separating_riscv-CMOs_and_riscv-CMOs-discuss.md Modified: separating_riscv-CMOs_and_ris

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[riscv-CMOs:master] New Comment on Issue #15 Use cases for CMOs - collect By ubc-guy: I've used CMOs to assist coherence in hybrid systems, where some processors are coherent but accelerators are not

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[riscv-CMOs:master] New Comment on Issue #18 Invited Talks - collect suggestions By dkruckemyer-ventana: My notion of interfaces includes semantics, so yes, I was expecting a full discussion from a li

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Are you saying that the cache mgmt operations are on ranges varying from a fraction of a line to something that might cover at most 5 lines? (assuming 64B lines and worst case misalignment for 256B ra

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1 New Commit: [riscv-CMOs:master] By Andy Glew (Dell ) <surfbook@...>: fbcef65102fc: Derek Williams, IBM, argument against address ranges for RISC-V CMOs Added: discussion-files/RISC_V_range

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