[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By a4lg: To whom it may concern, (Cc: @asb @aswaterman @jrtc27 @nelson-chu @kito-chen

#github #risv #CMOs

Fix a typo. From: tech-cmo@... <tech-cmo@...> on behalf of Liang Yin via lists.riscv.org <lyin=tenstorrent.com@...> Date: Friday, March 18, 2022 at 11:38 AM To: Guy

>> isn't this the role of non-normative text? Right. I am new to the forum. Just check the ISA spec, and it does look like this is covered through non-normative text sections. >> that is a desirable o

Ditto what Guy said. -Phil

Look at the MakeUnique and MakeInvalid transactions in the AMBA ACE protocol (compare to the corresponding CleanUnique and CleanInvalid transactions which do require that main memory be updated).

isn't this the role of non-normative text? that is a desirable optimization, but I don't know if any systems can/do support this. most cache coherence protocols support invalidations which always trig

On Thu, Mar 17, 2022 at 11:38 AM Guy Lemieux <guy.lemieux@...> wrote: [snip] is there a cbo.zero.noalloc instruction, which writes 0s all the way through to memory (without allocating in the cac

[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By a4lg: GNU Binutils adopted textual format '(rs1)' and '0(rs1)'. Textual format 'rs

#github #risv #CMOs

[riscv-CMOs:master] New Comment on Issue #47 Textual format for cbo.* asm operands - '(rs1)' and '0(rs1)' vs 'rs1' By a4lg: GNU Binutils adopted textual format '(rs1)' and '0(rs1)'. Textual format 'rs

#github #risv #CMOs

The architecture spec generally should avoid implementation details. On the other hand, it might be useful to have a dedicated section for implementation guidance as that would help the code/IP sharin

Yes, all that is true, and you point out all the work someone would have to do to take advantage of it. and someone could take advantage of that to avoid writeack (e.g. if it displace dirty data, of B

David, thank you for your service. I hope someone can be found to Chair the TG, as I would like to see continued progress. Unfortunately my schedule and experience leaves me short of being able to do

not really. if the cpu already has exclusive access to the block, no data transfer or permission is required, so there is no fetch to save with cbo.zero. if the cpu already has shared access, again no

Hi all, Just a reminder about nominations for chair of the CMO TG. The deadline is March 23rd (inclusive). On a related note, I plan to step down as chair, and after consultation with the privileged I

The intent of cbo.zero is to signal a write of zeros to a full cache block. As mentioned previously, implementations can take advantage of that intent in a number of different ways that may be differe

Can't cbo.zero also optimize away fetching a line from memory, since it will overwrite it completely? That also saves a ton of power and latency.

Cbo.zero writes a full block of all zeroes (but just zeroes). This corresponds to common use cases in, for example, Linux-based systems. A similar non-vector/simd instruction exists in other architect

Hi All, I’m forwarding on these questions from Kai liu (who is on this mailing list now). I did my best to answer #1 but I’ll let the experts weight in on both these queries. Cheers, Stephano -- Steph

Hi all, Nothing to discuss this week so I'm canceling the meeting. Just a reminder that nominations are open for Chair. Please reply to the email titled "Call for Candidates" to nominate yourself or s

Hi all, As per the policy governing chairs and vice chairs, we are holding a call for candidates for the position of Chair for the Cache Management Operation (CMO) Task Group. To nominate yourself or