[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By brucehoult: My understanding of the intent of the RVA ISA Profiles is that Linux distro

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By cmuellner: A plausible and sensible scenario would be that upstream will support all th

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By gfavor: My understanding of the intent of the RVA ISA Profiles is that Linux distros wi

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By dkruckemyer-ventana: FWIW, this profile option, Zic64b, also indicates the cache block

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1 New Commit: [riscv-CMOs:master] By David Kruckemyer <dkruckemyer@...>: 8e8a8e01e1e2: Create cmobase-v1.0.1.pdf Added: specifications/cmobase-v1.0.1.pdf [riscv-CMOs:master] New Comment o

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By dkruckemyer-ventana: My actual preference is "must" but for some reason I thought "shall" was preferred more gene

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By cmuellner: The CBO spec says: """ 2.7. Software Discovery The initial set of CMO extens

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By brucehoult: I don't know if we have our own document specifying wordings such as this. I think most groups follow

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By kito-cheng: @cmuellner thanks for the info, I didn't realized that CBO operation size m

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By cmuellner: We were discussing that as part of the kernel support for CBO. It was agreed

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By a4lg: My intent (on GNU Binutils) is, The encoding does not allow specifying actual offset (effectively, only off

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Don't we already have that capability with the mconfigptr extension, and the config-struct schema which encode that data it points to?? It isn't an instruction, it is a database which is pointed to by

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By ubc-guy: in the vector spec, software needs to know the maximum length of a vector that

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By ubc-guy: am I misunderstanding the phrase "any expression that computes the offset shall evaluate to zero" ? what

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By ubc-guy: am I misunderstanding the phrase "any expression that computes the offset shall evaluate to zero" ? what

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By a4lg: LGTM. Proposed version number (1.0.1) is nice because it wouldn't change the extension version itself.

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By cmuellner: LGTM

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[riscv-CMOs:master] New Comment on Issue #48 How to discover the information of cache block size by software? By kito-cheng: I run into problem when I tried to implement __builtin___clear_cache with c

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[riscv-CMOs:master] New Comment on Pull Request #49 New textual form By a4lg: As better PR as published as #51, I'll close this. [riscv/riscv-CMOs] Pull request closed by a4lg: #49 New textual form Th

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[riscv-CMOs:master] New Comment on Pull Request #51 update instruction descriptions By kito-cheng: As a GNU toolchain maintainer, LGTM, thanks! and thanks @a4lg push this forward :)

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