Formal Specification Task Group tech-formalspec@lists.riscv.org

Group Description

This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness. It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers.  It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs. [ This work is closely related to and complementary to the work of the  Memory Model Task Group ]

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