Formal Specification Task Group

Group Description

This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness. It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers.  It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs. [ This work is closely related to and complementary to the work of the  Memory Model Task Group ]

Group Information

  • 93 Members
  • 193 Topics, Last Post:
  • Started on

Group Settings

  • This is a subgroup of main.
  • All subscribers can post to the group.
  • Posts to this group do not require approval from the moderators.
  • Messages are set to reply to sender.
  • Subscriptions to this group require approval from the moderators.
  • Archives are visible to subscribers only.
  • Wiki is visible to subscribers only.
  • Members can edit their messages.
  • Members can set their subscriptions to no email.

 or  Log In If You Are Already A Member

Message History

Group Email Addresses