Hi Furquan, Yes, let's do that. I will setup a meeting on Monday 27th 2022. We can continue the discussion later if we can not finish in an hour. Thanks! Sunil

You have been invited to the following event. Ad-hoc ACPI ECR Review meeting When Mon Jun 27, 2022 9:30pm – 10:30pm India Standard Time - Kolkata Joining info Join with Google Meet meet.google.com/dao

Hi All, Please review below Engineering Change Request (ECR) to update the ACPI spec for enabling basic ACPI support for RISC-V. 1) Add INTC structure in MADT Table - https://docs.google.com/document/

All, As per the policy governing chairs and vice chairs, we are holding a call for candidates for the positions of CHAIR and VICE-CHAIR for the OS-A SEE TG. To nominate yourself or another member of t

It seems to me that the rationale and summary of the extension is insufficient, and non-normative commentary is lacking. The ensuing mailing list discussion suggests that there are additional requirem

That is because it is useful to have debug console output when porting a hypervisor or baremetal code to a new board. Of course, if a hypervisor is already available for the board, then it would be ju

Thanks for starting to close this gap. I miss a discussion of the conflicts that can arise if the configuration of the serial console is changed by the caller. Do we need an ecall that closes the SBI

Hi Anup, Here are my thoughts: * Guest memory access: I think this would be the first SBI extension to require access to guest memory. This needs to be considered carefully, but I think the higher ban

Should we keep this simple in the SBI - only have register based inputs - to send and receive 1 byte in each call? Keeping it a simple out_byte or in_byte - a serial port like interface seems the simp

Hi All, Below is the draft proposal for SBI Debug Console Extension. Please review it and provide feedback. Thanks, Anup Debug Console Extension (EID #0x4442434E "DBCN") ==============================

There are variety of ways in which supervisor software can use tarea_offset: 1) Use lock to serialize access to shared memory and always use fixed offset (maybe zero) from all HARTs 2) No lock to prot

Thanks, it will be nice to drop putchar. What is the motivation for `area_offset`? Will the supervisor use different offsets for different harts? What are the advantages and disadvantages of the offse

Hi All, My apologies for the long email up front. I hope people find this useful as well as a starting point for a broader discussion in how all these pieces fit together within RISC-V. There are impl

Hi All, I'm cross posting to tech-unixplatformspec@ and tech-os-a-see@ lists because there wasn't sufficient overlap in membership to get the proper visibility. I had proposed a charter that can be fo

Hi Folks, My apologies for the tardy follow up. I put together a proposed charter for the OS-A SEE TG. I used a Google doc for quick feedback, but email also works. Feel free to critique and throw tom

Hi All, I wanted to point out that we have GitHub repositories and a mailing list for OS-A SEE (Supervisor Execution Environment) TG. Please join if you are interested. GitHub Admin: https://github.co