Tech: Software Overlay Task Group tech-overlay@lists.riscv.org

Software Overlay Task Group

 

github: https://github.com/riscv/riscv-overlay

Motivation

In the early days of embedded computing there was a technique to load code in Real-Time at the moment it was needed for execution. Back then memory was expensive in all aspects. Similarly, today, IoT devices are very restricted with memory size and power. Due to those needs, the need for reviving the overlay concept, with RISC-V ISA, was needed along with RISC-V toolchain to support it.
 

Charter

The Software Overlay TG will specify the requirements for the software overlay feature, both from the FW manager engine and from toolchain aspects, all of which will be based on the current RISC-V ISA and extensions.

 

Deliverable 

Full operation software stack to be part of RISC-V toolchain, includes runtime software and toolchain support.

Initial  Roadmap (by Phases)

Gather
  1. Gathering specification and requirements: what we wish this feature to contain
  2. Making generic software requirements to be approved by the TG
Design
  1. Establish a software spec based on the requirements 
  2. Designing RT FW, using RISC-V ISA
  3. Designing Toolchain usage
  4. Write HLD (High-level design) for the RT engine
Implementation
  1. Implementation and LLD (low-level design)
  2. Deployment 
  3. Write Test suite
  


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