- Status of v1.12 privileged specification
Re: Status of v1.12 privileged specification
On Tue, Jul 26, 2022 at 8:05 AM Greg Chadwick <gac@...
I appreciate no guarantees are possible but is it anticipated that the final v1.12 of the RISC-V privileged specification will be the v. 20211203 currently listed on the RISC-V website (https://riscv.org/technical/specifications/
) along with copy edits and the relevant already ratified extensions integrated (Smepmp, Smstateen, Sstc) as new chapters as the Svinval, Svnapot, Svpbmt extensions already are?
From that version onwards the ratified chapters are frozen other than "typo" corrections and clarifications. The plan is for all Priv-related ratified extensions to be integrated into the Priv document (i.e. to have them all in one document), and for the Priv (and Unpriv) documents to be converted to adoc and to the new RVI adoc format. These are active works in progress. In general every new extension will be a separate new chapter.
Am I right in my understanding that support of new extensions for a particular implementation is determined via the (as yet to be defined) structure pointed to by the mconfigptr CSR
and that any instructions introduced by one of those extensions should cause an illegal instruction exception where that extension isn't supported?
The current ISA arch specs do not require that unimplemented instructions result in an Illegal Instruction trap. That is left for an ISA Profile or a Platform to recommend or mandate.
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