Re: [RISC-V] [tech-virt-mem] Help needed on physical address issues


The virt-mem list is quiescent and will go away shortly. Please send questions like this to the governing committee (priv). I have plus'ed them in.


On Tue, Aug 9, 2022 at 3:24 AM Ke Chai <ck.rickytino@...> wrote:
To whom it may concern,

Hello! I am currently working on a RV64 CPU featuring Sv48 and Sv39, and came up with several questions that none of the existing documents have clearly specified: 

1. The physical address width in my RV64 implementation is 50 bits. If a 56-bit address is generated (e.g. from a leaf PTE's PPN concatenates an address offset, or from a physical address translated directly from a virtual address under M mode) with non-zero at the high bits (i.e. bits 55-50), should I just ignore the high bits, or report an access fault exception (assuming this is recognized as an vacant address space during a PMA check)?

2. Is there any way the M-mode software can know how many physical address bits are implemented on this implementation?

3. I saw a sentence on the RISC-V privileged architecture document at the end of section 4.3.2:
"The algorithm does not admit the possibility of ignoring high-order PPN bits for implementations with narrower physical addresses". What does "does not admit the possibility" supposed to mean? What action would be taken by hardware if the high-order PPN bits are not zero?

Really looking forward to someone who can give me some clarification on this! 

Thank you so much,
Ricky Chai

Join to automatically receive all group messages.