Still one little question: What happens when MMU is disabled (VA=PA) and bit [63:56] is not zero? Still report Access Fault? Or are we assuming the full-PA width is 64 or 56?
My earlier statement about PAs conceptually or architecturally being viewed as zero-extended values makes them agnostic to implemented PA size. In general, and irrespective of where a PA comes from (e.g. from M-mode, Bare translation mode, or a translated mode), one conceptually has a 64-bit PA.
If a PA is the result of translation, then one has a 56-bit zero-extended PA, i.e. the translated 56-bit PA from the leaf PTE is zero-extended up to 64 bits. Also, no matter what, the entire PPN field is used to create the final overall PA.
If a PA is the result of calculation by a register instruction, then one has a full 64-bit PA (assuming RV64). The full 64-bit calculated value becomes the PA.
At the end of the day one always has a 64-bit PA that is then checked by PMAs. So if a system only "implements" an N-bit PA space, then all 64-N msb's of a PA must be zeroes - as enforced by having a "vacant" PMA region that covers the 64-N bits of PA space and causes an Access Fault. Practically speaking this allows address-specific datapaths to only be 64-N bits wide since one can check for all high PA bits being zeroes right away (and not carry them forward).