| Can a virtual paged be mapped to addresses that cross PMA regions? For example, is it acceptable to map a 1GB page such that half its physical addresses have the (e.g.) cacheableOn Fri, 12 Aug 2022 10:35:15 -0700, "Greg Favor" <gfavor@...> said:
| attribute but the other half of physical addresses are uncacheable? You could think about this with every attribute: vacant, idempotent, etc.
| This sounds odd, but the ISA does not explicitly allow or forbid it. Is it something that must to be supported? If so, are there example use-cases?
| The PMA architecture allows a lot of implementation flexibility - including for example having small 4B regions. In that example one could easily have one 4KB page overlap multiple
| PMA regions.
| Conversely, in a typical OS-A class system using demand-paged virtual memory, the implementor will probably choose to have a minimum 4KB granularity to PMA regions. Although this
| still allows 2MB, 1GB, and 512GB pages to overlap multiple PMA regions. (Which in typical TLB implementations leads to what some would call "atomization" of page mappings into
| smaller TLB entry mappings.)
Even in a RISC-V OS-A platform, the implementor might be stuck with
using IP peripherals where PMAs vary at the sub-page granularity.
| In short, if a page overlaps multiple regions, then that needs to be handled properly. Typically any given load/store/ifetch/implicit access that is being checked will fall in one
| page and in one PMA region - in which case the behavior is obvious. But if that access straddles multiple pages and/or PMA regions, then each byte of the access must pass its MMU
| and PMA checks for the whole access to be allowed.
We have some text for this in some places, but these concepts should
really be factored out somewhere central.