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Fast-track extension proposal V3 for "Sv32 Svpbmt"

Guo Ren
 

Hi all,
 
Here is the third version of the proposal.
 
V2: https://lists.riscv.org/g/tech-privileged/message/1079
V1: https://lists.riscv.org/g/tech-privileged/message/1051
 
This posting to this email list starts an initial review period for people to provide feedback, questions, comments, etc.
 
Thanks,
Guo Ren

========================================================================
 
=======================  Supervisor Extension Additions  ========================
\subsection{``Svpbmt32'' Extension for Page-Based Memory Types}
\label{sec:translation}

Svpbmt32 support is being added to allow the two highest bits of a PTE
to be used as PBMT instead of PA[33:32] for Sv32. The S-mode and
G-stage address translation under this extension are controlled by the
menvcfg.PBMTE. The VS-stage address translation under this extension
is controlled by henvcfg.PBMTE and indirectly by menvcfg.PBMTE.

\begin{commentary}
For example, consider an RV32 system supporting Svpbmt32 and
Hypervisor Extension (Chapter~\ref{hypervisor}). When menvcfg.PBMTE=1,
Svpbmt32 is available for S-mode and G-stage address translation. When
henvcfg.PBMTE=1, Svpbmt32 is available for VS-mode address translation.
\end{commentary}

Sv32 virtual address:
| 31  22 | 21  12 | 11        0 |
  VPN[1]   VPN[0]   page offset
    10       10         12
 
Sv32 physical address with Svpbmt: 
| 31  22 | 21  12 | 11        0 |
  PPN[1]   PPN[0]   page offset
    10        10         12
Sv32 page table entry with Svpbmt: 
| 31 30 | 29  20 | 19  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  PBMT   PPN[1]   PPN[0]   reserved for SW   D   A   G   U   X   W   R   V
========================================================================
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