Fast-track extension proposal for H/W PTE A/D updating
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Ved Shanbhogue
Greetings ! We are submitting for your consideration an extension for HW PTE A/D updating (Svadu) controls. As you might recall the privileged specification defines two HW behaviors for PTE A/D bits if they are 0 when required to be 1: - to cause a (guest) page fault - to update the A and/or D bits This extension provides controls to select between the behaviors. Please find the PDF and source here: https://github.com/riscv/riscv-svadu Please add comments/issues in github or to this thread. regards ved |
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