Re: Fast-track extension proposal for H/W PTE A/D updating
I concur; it is not apparent from this spec what is different vs. the long-existing implementation option to have hardware A/D updating. Is it only the new CSR bits?toggle quoted message Show quoted text
This constraint appears new:
> Svadu extension requires the page tables to be located in cacheable main memory PMA regions.
What happens if they are not? Access fault? Unspecified?