Re: Fast-track extension proposal for H/W PTE A/D updating

Scott Johnson

I concur; it is not apparent from this spec what is different vs. the long-existing implementation option to have hardware A/D updating. Is it only the new CSR bits?

This constraint appears new:

> Svadu extension requires the page tables to be located in cacheable main memory PMA regions.

What happens if they are not? Access fault? Unspecified?

On Oct 26, 2022, at 7:30 PM, John Ingalls <john.ingalls@...> wrote:

> "The A and D bits are managed by these extensions as follows: ..."

Does the scope of this extension include changing, constraining, or clarifying the behaviors already described in the Privileged ISA spec?  If yes, then I will follow up with more.  If not, then I suggest not opening that can of worms.  To limit this to just the CSR bits, can we say this instead for the content on page 3, and remove all the re-defining text?

"The A and D bits are managed by this extension as described in as specified in the Supervisor-Level ISA extension (section 4.3) and as modified by the hypervisor extension (section 8.5.1)."

On Wed, Oct 26, 2022 at 4:27 PM Ved Shanbhogue <ved@...> wrote:
Greetings !

We are submitting for your consideration an extension for HW PTE A/D updating (Svadu) controls.

As you might recall the privileged specification defines two HW behaviors for PTE A/D bits if they are 0 when required to be 1:
- to cause a (guest) page fault
- to update the A and/or D bits 

This extension provides controls to select between the behaviors.

Please find the PDF and source here:

Please add comments/issues in github or to this thread.


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