Re: Fast-track extension proposal for H/W PTE A/D updating
Allen Baum
This is more than just clarifying and naming. It also defines a specfic WARL control bit. in an existing, defined CSR. Individual WARL CSR bits can be RW, RdOnlyZero, or RdOnly1 (WARLÂ *fields* can have infinitely more complex behaviors). In the discussion, I believe it was also stated that RdOnly 1 was disallowed by this CSR bit, which "solves" the problem of mixing and matching implementations that do it both ways.
On Thu, Oct 27, 2022 at 9:00 AM Ved Shanbhogue <ved@...> wrote: On Thu, Oct 27, 2022 at 08:07:15AM +0200, Roger Espasa wrote:
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