Re: Fast-track extension proposal for H/W PTE A/D updating

John Ingalls

On Thu, Oct 27, 2022 at 11:06 AM Allen Baum <allen.baum@...> wrote:
This is more than just clarifying and naming. It also defines a specfic WARL control bit. in an existing, defined CSR.
Individual WARL CSR bits can be RW, RdOnlyZero, or RdOnly1 (WARL *fields* can have infinitely more complex behaviors).
In the discussion, I believe it was also stated that RdOnly 1 was disallowed by this CSR bit,
which "solves" the problem of mixing and matching implementations that do it both ways.

On Thu, Oct 27, 2022 at 9:00 AM Ved Shanbhogue <ved@...> wrote:
On Thu, Oct 27, 2022 at 08:07:15AM +0200, Roger Espasa wrote:
>I would concur with Scott above. Clarifications to the spec belong in the
>spec itself, not inside an extension. If the Architecture Review Committee
>suggested otherwise, is it because the clarifications only pertain to the

There were two motivations. One to name the specified behavior
and second to provide a control to select between the two
specified behaviors.

The specification for hardware updating of A/D bits existed
along with the specification for causing a (guest)page fault.
Whereas the behavior to cause a page-fault has an extension
name Ssptead, the behavior for hardware updating did not have
an extension name.

Hardware updating behavior is is now named Svadu and the
specification related to Svadu is now associated it. In the
process a few clarifications were added as noted and Svadu
provides the controls to select between the two specified
behaviors for A/D bits.


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