Question about CSR hedeleg and hideleg

Oscar Jupp

To whom it may concern,
I have a question about CSR hedeleg and hideleg.
The ISA  Manual said: "The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest." 
I would like to know in what scenario or under what requirements, it is necessary to delegate the interrupt or exception to the VS mode? What would be the impact of making all bits of these two CSRs read-only zeros?
Any help would be greatly appreciated!
Oscar Jupp

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