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Re: Question about guest external interrupt

Oscar Jupp
 

Dear Anup Patel,
Thank you very much for your reply.
 I would like to continue to ask: If GEILEN is 0, CSR hgeip and hgeie will always be all zero. Then, hip.SGEIP is always 0. You said: “software (i.e. hypervisor) can still inject external interrupts using hvip CSR. “ But hvip CSR can only make hip.VSSIP, hip.VSTIP and hip.VSEIP raised. It can not make hip.SGEIP be “1”. How does the implement recognize that this is a guest external interrupt.

Regards,
Oscar Jupp

---- Replied Message ----
From Anup Patel<apatel@...>
Date 11/17/2022 11:56
To Oscar Jupp<jupposcar@...>
Cc tech-privileged@...<tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about guest external interrupt
On Thu, Nov 17, 2022 at 9:07 AM Oscar Jupp <jupposcar@...> wrote:


To whom it may concern,
I have a question about guest external interrupt.
The privileged ISA said: "GEILEN may be zero". If GEILEN is zero, is the implementation unable to receive guest external interrupts at all? Or can it be injected by software means?

If GEILEN is zero then there are no guest external interrupts but
software (i.e. hypervisor) can still inject external interrupts using
hvip CSR. In other words, software-injected external interrupts are
always available to a hypervisor using H-extension.

Regards,
Anup

Any help would be greatly appreciated! Thank you
Regards
Oscar Jupp
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