Re: Question about CSR hedeleg and hideleg
Dear Paul Donahue,
Thank you very much.
I would like to ask another question.
The VS level external interrupt has been delegated to the VS level (That is, mideleg = 1 and hideleg = 1). When an VS level external interrupt comes in, only vsip.SEIP will be set. The sip.VSEIP and mip.VSEIP are both 0. Is it right?
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The idea is that interrupts should be handled in the mode they target or a more privileged mode, not a less privileged mode. The hypervisor can optionally send VS interrupts to VS mode but the hardwired bits prevent it from sending M or S interrupts to VS mode.
On Thu, Nov 17, 2022 at 4:22 AM jupposcar <jupposcar@...> wrote: