Dear Paul Donahue,

Thank you very much for your reply！

I have another question about hideleg。The privileged ISA said: “Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.” 

How about the other bits? Bits 11,7, and 3 (corresponding to the standard M-level interrupts) are read-only zeros? Why?

Regards,

Oscar Jupp

	jupposcar
jupposcar@...

---- Replied Message ----

From	Paul Donahue<pdonahue@...>
Date	11/17/2022 01:39
To	Oscar Jupp<jupposcar@...>
Cc	<tech-privileged@...>
Subject	Re: [RISC-V] [tech-privileged] Question about CSR hedeleg and hideleg

For instance, page faults should normally be delegated to the operating system that manages the page tables rather than handling it in a higher mode which doesn't know anything about the OS's memory management.  So if page tables are managed in S/HS, you don't want to handle page faults in M mode and you use medeleg to do the delegation.  Similarly, if a guest (VU or VS) gets a page fault then you want to use hedeleg to delegate to the guest OS which is managing VS-stage page tables.

-Paul

On Wed, Nov 16, 2022 at 3:28 AM Oscar Jupp <jupposcar@...> wrote:

To whom it may concern,

I have a question about CSR hedeleg and hideleg.

The ISA  Manual said: "The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest." 

I would like to know in what scenario or under what requirements, it is necessary to delegate the interrupt or exception to the VS mode? What would be the impact of making all bits of these two CSRs read-only zeros?

Any help would be greatly appreciated!

Regards

Oscar Jupp