Re: Question about CSR hedeleg and hideleg


Oscar Jupp
 

Dear architect,
Thanks! I learned a lot from you.
I used to think that mip is used to indicate the summary of interrupts that need to be responded in M state, sip is used to indicate the summary of interrupts that need to be responded in S state, and vsip is used to indicate the summary of interrupts that need to be responded in VS state. It seems I misunderstood.
Regards,
Oscar Jupp


---- Replied Message ----
From Scott Johnson<scott.johnson@...>
Date 11/18/2022 11:37
To Oscar Jupp<jupposcar@...>
Cc tech-privileged@...<tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about CSR hedeleg and hideleg
No.

Assuming bit 10 of hideleg is one, vsip.SEIP is an alias of hip.VSEIP.

mip.VSEIP is an alias of hip.VSEIP.

Bit 10 in mideleg is read-only one, so mip.VSEIP is visible as sip.VSEIP.

Therefore both sip.VSEIP and mip.VSEIP will be 1.

An implementation really only needs to have one set of state for mip and that will cover all the other *ip CSRs, which are all views into that one set of bits.


On Nov 17, 2022, at 9:21 PM, Oscar Jupp <jupposcar@...> wrote:

Dear Paul Donahue,
Thank you very much.
I would like to ask another question.
The VS level external interrupt has been delegated to the VS level (That is, mideleg[10] = 1 and hideleg[10] = 1). When an VS level external interrupt comes in, only vsip.SEIP will be set. The sip.VSEIP and mip.VSEIP are both 0. Is it right?

Regards,
Oscar Jupp

---- Replied Message ----
From Paul Donahue<pdonahue@...>
Date 11/18/2022 03:13
To jupposcar<jupposcar@...>
Cc tech-privileged@...<tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about CSR hedeleg and hideleg
The idea is that interrupts should be handled in the mode they target or a more privileged mode, not a less privileged mode.  The hypervisor can optionally send VS interrupts to VS mode but the hardwired bits prevent it from sending M or S interrupts to VS mode.


-Paul


On Thu, Nov 17, 2022 at 4:22 AM jupposcar <jupposcar@...> wrote:
Dear Paul Donahue,
Thank you very much for your reply!
I have another question about hideleg。The privileged ISA said: “Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.” 
How about the other bits? Bits 11,7, and 3 (corresponding to the standard M-level interrupts) are read-only zeros? Why?

Regards,
Oscar Jupp


---- Replied Message ----
From Paul Donahue<pdonahue@...>
Date 11/17/2022 01:39
To Oscar Jupp<jupposcar@...>
Cc <tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about CSR hedeleg and hideleg
For instance, page faults should normally be delegated to the operating system that manages the page tables rather than handling it in a higher mode which doesn't know anything about the OS's memory management.  So if page tables are managed in S/HS, you don't want to handle page faults in M mode and you use medeleg to do the delegation.  Similarly, if a guest (VU or VS) gets a page fault then you want to use hedeleg to delegate to the guest OS which is managing VS-stage page tables.


-Paul


On Wed, Nov 16, 2022 at 3:28 AM Oscar Jupp <jupposcar@...> wrote:
To whom it may concern,
I have a question about CSR hedeleg and hideleg.
The ISA  Manual said: "The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest." 
I would like to know in what scenario or under what requirements, it is necessary to delegate the interrupt or exception to the VS mode? What would be the impact of making all bits of these two CSRs read-only zeros?
Any help would be greatly appreciated!
Regards
Oscar Jupp



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