The Sstc specification has this text (referring to whether STIP is writable):
If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to S-mode. If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp.
Can you please clarify what is meant by implemented here? Andrew Waterman pointed me at a statement in the Privileged Specification that indicated that implemented implicitly meant implemented and enabled, but that doesn't seem fully relevant here, for the reason that if the Sstc extension is present then stimecmp is always accessible at M-mode, so in some sense this extension is always enabled.
It feels that, for software backwards-compatibility, STIP should be writeable by M-mode if menvcfg.STCE=0 and read-only if menvcfg.STCE=1, but I am unsure whether this is the intention.
A similar clarification is needed for VSTIP, when the Hypervisor is implemented.