“Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisorlevel timer interrupts. If implemented, STIP is read-only in sip, and is set and cleared by the
execution environment.
Bits sip.SSIP and sie.SSIE are the interrupt-pending and interrupt-enable bits for supervisorlevel software interrupts. If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller.”
What does “execution environment“ refer to in the description of sip.STIP? Is the M-level software? Or is it a pure hardware platform like an interrupt controller? What does "platform-specific interrupt controller" refer to in the description of sip.SSIP? I think that inter-core interrupts are implemented through bus configuration memory-mapped registers? Why does it need an interrupt controller?
