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Re: Quetion about SSTC

Greg Favor
 

Per Priv section 2.1 and Table 2.1, the CSR numbers encodes the lowest privilege level that can access the CSR.  That level and all higher levels can access the CSR.

So the first row of red should be M, HS; and the second row of red should be M, HS, VS.  In general, these CSRs are never accessible by U/VU privilege modes.

Greg

On Mon, Nov 21, 2022 at 5:35 AM Oscar Jupp <jupposcar@...> wrote:
Dear architect,
The stimecmp / vstimecmp” Extension said:
"When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode
raises an illegal instruction exception, STCE in henvcfg is read-only zero, and STIP in mip and sip reverts to its
defined behavior as if this extension is not implemented. 
When STCE in menvcfg is one but STCE in henvcfg is zero, an attempt to access stimecmp (really vstimecmp)
when V = 1 raises a virtual instruction exception, and VSTIP in hip reverts to its defined behavior as if this
extension is not implemented."

So I made the following table to show the conditions of accessing stimecmp and vstimecmp when menvcfg.STCE, henvcfg.STCE and V take different values.
The blue words in the table are the access conditions I understand. If there are any mistakes, please point it out for me.
The red words in the table are not clear to me, please clarify what is the access conditions of each privilege level.

menvcfg.STCE
henvcfg.STCE
V
Access the CSR with number 0x14D(stimecmp)
Access the CSR with number 0x24D(vstimecmp)
0
0(read-only zero)
0 or 1
Except M-level can access, other privilege level access will generate illegal instruction exception.
1
0
0
M,S(HS), and U can all access
M, S(HS), and U ????
1
0
1
VS and VU will generate virtual instruction exception
VS and VU will generate virtual instruction exception
1
1
0
M,S(HS), and U level can all access
M，S(HS) can access，U-level will generate illegal instruction exception.
1
1
1
VS and VU????????
VS and VU will generate virtual instruction exception

Regards,
Oscar Jupp
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