Without a deep understanding of these particular bits (and Greg will correct me if I'm wrong) there are some general rules that should apply

(I am unaware of any exceptions to this off the top of my head, but if they are anywhere, they'd probably be in the interrupt and hypervisor CSRs): 

 A bit that is RW accessible to a lower privilege mode should always be RW at a higher privilege mode (though it may be accessed at a different address because of the way hypervisor extension works)

  If the CSR is accessible to the accessing mode at all, and is not in the ReadOnly CSR ranges, then

  if a bit is described as an alias,      then it should be read/write if they are read/write at the higher privilege level

  if a bit is described as an shadow, then it should be read-only  even if they are read/write at the higher privilege level

  A CSR which is described as a "restricted view" would have some bits that aliased at a higher privilege level, and be read-only zero at lower privilege levels.

On Sat, Nov 26, 2022 at 10:56 PM Greg Favor <gfavor@...> wrote:

On Sat, Nov 26, 2022 at 8:41 PM jupposcar <jupposcar@...> wrote:

1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” 

But I don’t know they are read-only aliases ? or read-write aliases ? In other word, Can the CSR instruction  with the CSR number 0x344 (mip) modify these bits?

Per Priv section 2.2, 0x344 is read/write.  And hip is also read-write.  So the mip aliases of these hip bits are also read/write in mip.

 

Or only CSR instruction with the CSR number 0x644 (hip) can modify these bits?

2. The ISA said : “If implemented, SEIP is read-only in sip."(Priv section 4.3.1)

It means sip.SEIP is read-only for S-mode. Similarly, is vsip.SEIP read-only for VS-mode ?

First, I think you mean section 5.1.3 in the latest draft of the Priv spec.  And yes, you're correct.

 

Greg