Question about supervisor interrupt in M mode
Priv spec section 22.214.171.124 write:
“When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. Interrupts for lower-privilege modes, w<x are always globally disabled regardless of the setting of any global wIE bit for the lower-privilege mode."
So I think when a hart is executing in M mode, supervisor timer interrupt is disabled.
However, Priv spec section 3.1.8 write:
“For example, if the supervisor timer interrupt (STI) is delegated to S-mode by setting mideleg, STIs will not be taken when executing in M-mode. By contrast, if mideleg is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode.”
Is it contradictory.