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Re: Question about supervisor interrupt in M mode

Oscar Jupp
 

Dear Allen,
Thank you for your replay.
How to understand next sentence: 

"Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE 
bit for the higher-privilege mode.”

Is it should be interpreted as:
“When xIE = 1,  Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE 
bit for the higher-privilege mode.”?

Regards,
Oscar Jupp

---- Replied Message ----
From Allen Baum<allen.baum@...>
Date 11/29/2022 21:24
To Oscar Jupp<jupposcar@...>
Cc tech-privileged@...<tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about supervisor interrupt in M mode
I think (and will be corrected if wrong) that the sentence should be interpreted as
When xIE=0, Interrupts for lower-privilege modes, w<x are always globally disabled regardless of the setting of any global wIE bit for the lower-privilege mode."


On Tue, Nov 29, 2022 at 3:50 AM Oscar Jupp <jupposcar@...> wrote:
Dear architect, 
Priv spec section 3.1.6.1 write: 
“When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. Interrupts for lower-privilege modes, w<x are always globally disabled regardless of the setting of any global wIE bit for the lower-privilege mode."

So I think when a hart is executing in M mode, supervisor timer interrupt is disabled.

However, Priv spec section 3.1.8 write: 
“For example, if the supervisor timer interrupt (STI) is delegated to S-mode by setting mideleg[5], STIs  will not be taken when executing in M-mode. By contrast, if mideleg[5] is clear, STIs can be taken  in any mode and regardless of current mode will transfer control to M-mode.”

Is it contradictory.

Regards,
Oscar Jupp

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