Re: Question about supervisor interrupt in M mode


Jeff Scott
 

Yep, think of mti as first timer interrupt and sti as second timer interrupt.

 

A pseudocode equation for “enabled” in the spec would make this easier.  I think if you search on previous Summit proceedings, there was a presentation a long time ago that showed the equations.

 

Jeff

 

From: tech-privileged@... <tech-privileged@...> On Behalf Of Scott Johnson via lists.riscv.org
Sent: Tuesday, November 29, 2022 10:05 AM
To: tech-privileged@...
Subject: [EXT] Re: [RISC-V] [tech-privileged] Question about supervisor interrupt in M mode

 

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Oscar, what you are missing is that STI, despite its name, is not for a lower-privilege mode when mideleg[5]==0. In that case the STI is destined for M-mode and therefore can be taken in any privilege mode.

To correct your statement: When a hart is executing in M mode, supervisor timer interrupt is disabled if mideleg[5]==1.

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