Re: Question about supervisor interrupt in M mode
|
Oscar Jupp
Dear Scott， Thank you for your reply. Do you mean that : “Supervisor timer interrupt if mideleg[5]==0 is a interrupt for M mode. Supervisor timer interrupt if mideleg[5]==1 is a interrupt for S mode.”? If yes, how to understand the next sentences: "Interrupts for
higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE
bit for the higher-privilege mode.” My understanding is as follows： suppose x = S mode, y = M mode. When a hart is executing in S mode, supervisor timer interrupt is always enabled if mideleg[5]==0 regardless of the setting of the global mIE bit. But it's weird, sip.STIP is read-only zero when the mideleg[5]==0. It is enabled for what? Regards, Oscar Jupp
---- Replied Message ----
Oscar, what you are missing is that STI, despite its name, is not for a lower-privilege mode when mideleg[5]==0. In that case the STI is destined for M-mode and therefore can be taken in any privilege mode.
To correct your statement: When a hart is executing in M mode, supervisor timer interrupt is disabled if mideleg[5]==1. |
||||||||
|
|
