Re: Question about supervisor interrupt in M mode
Thank you for your reply.
Do you mean that :
“Supervisor timer interrupt if mideleg==0 is a interrupt for M mode.
Supervisor timer interrupt if mideleg==1 is a interrupt for S mode.”?
If yes, how to understand the next sentences:
"Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE
bit for the higher-privilege mode.”
My understanding is as follows：
suppose x = S mode, y = M mode.
When a hart is executing in S mode, supervisor timer interrupt is always enabled if mideleg==0 regardless of the setting of the global mIE bit.
But it's weird, sip.STIP is read-only zero when the mideleg==0. It is enabled for what?
---- Replied Message ----
Oscar, what you are missing is that STI, despite its name, is not for a lower-privilege mode when mideleg==0. In that case the STI is destined for M-mode and therefore can be taken in any privilege mode.
To correct your statement: When a hart is executing in M mode, supervisor timer interrupt is disabled if mideleg==1.