Re: Question about supervisor interrupt in M mode
I'll stick my neck out again, and see if I get corrected again. This is the most difficult part of the spec for me to interpret.
Priv spec sec 3.1.9 says
(a) either the current privilege mode is M and the MIE bit in the mstatus
register is set, or the current privilege mode has less privilege than M-mode;
(a) either the current privilege mode is S and the SIE bit in the mstatus register is set, or the current privilege mode has less privilege than S-mode;
Since there is no sdeleg CSR, that term isn't used,
So sip[i] can't be set unless mideleg is set - there is a hidden term there - but I'll make it explicit here:
so: (Privmode!=M | Privmode==M & mstatus.MIE==1) & (mip[i]==1 & mie[i]==1) & mideleg[i]==0 --> trap to Mmode
(Privmode < S | Privmode==S & sstatus. SIE==1) & ( sip[i]==1 & sie[i]==1) & mideleg[i]==1 --> trap to Smode
Hypervisor complicates this a bit.
Now that I've probablyh misled you, let the corrections begin...
On Tue, Nov 29, 2022 at 11:24 PM Oscar Jupp <jupposcar@...> wrote: