Re: Question about supervisor interrupt in M mode

Scott Johnson

I think you’ve figured it out, but I’ve replied inline below anyway.

On Nov 30, 2022, at 1:24 AM, jupposcar <jupposcar@...> wrote:
Do you mean that :
“Supervisor timer interrupt if mideleg[5]==0 is a interrupt for M mode.
 Supervisor timer interrupt if mideleg[5]==1 is a interrupt for S mode.”?

Yes, exactly.

If yes, how to understand the next sentences:
"Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE 
bit for the higher-privilege mode.”

My understanding is as follows:
suppose x = S mode,  y = M mode.
When a hart is executing in S mode, supervisor timer interrupt is always enabled if mideleg[5]==0 regardless of the setting of the global mIE bit.

Yes, that’s correct.

But it's weird, sip.STIP is read-only zero when the mideleg[5]==0. It is enabled for what?

It will show up in mip.STIP which is where M-mode interrupts are seen.

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