On 5/18/20 5:10 PM, David Kruckemyer wrote:
That sounds a bit like a performance counter to me, but it does raise an interesting question whether "idempotent" in the architectural sense is idempotent in a mathematical sense (i.e. operations are repeatable with the same result) or in a broader sense
(e.g. inclusive of any side-effects even if the values at the location don't change).
I've always assumed the "non-idempotent" attribute meant that a read may not return the last value written or that repeated reads may not return the same value, not that the behavior included side-effects that are observable elsewhere. What is the consensus
I've always assumed that it included any side-effects that mattered to the program. It obviously does not include bringing the demise of a chip nearer with tiny amounts of electromigration. I don't think it includes incrementing
performance counters or shifting the results of predictors either. Not sure how many things actually fit between your definition and mine. Perhaps not many in real implementations.
On Mon, May 18, 2020 at 4:16 PM Rishiyur Nikhil <nikhil@...
Although I haven't seen any such implementation, I would imagine that a non-idempotent region that was, say, counting accesses to each address as a side-effect of each access may be a "benign" kind of non-idempotency for PTWs.
On Mon, May 18, 2020 at 6:26 PM Andrew Waterman <andrew@...
I have a simple question: does the architecture allow table walk accesses (reads or writes) to regions with the non-idempotent PMA?
The architecture doesn't explicitly disallow it, so the answer is probably "yes." However, I'm having a hard time understanding a system design in which such a table walk would be practical. Can someone provide a practical use-case for walking non-idempotent
If no such use-case exists, would people object to imposing a restriction on table walk accesses to locations with the non-idempotent PMA? Or at least a comment strongly suggesting that platforms won't support that behavior?
The specification machinery exists to allow implementations to impose such a restriction: "For systems with page-based virtual memory, I/O and memory regions can specify which combinations of hardware page-table reads and hardware page-table writes are
I'd support adding a note that permitting page-table accesses to idempotent regions is discouraged. Banning it seems a little harsh, though I see where you're coming from.