Re: Question about supervisor interrupt in M mode
I agree this took me several readings of the spec to understand this. Pseudo-code would have saved myself and others a lot of time.
Allen, thanks for taking the time to share this!
Can we add the final equation to the spec? It will save time for first time readers of the spec as well as everyone’s time answering questions in this area.
From: tech-privileged@... <tech-privileged@...> On Behalf Of Scott Johnson via lists.riscv.org
Sent: Wednesday, November 30, 2022 10:04 AM
To: Allen Baum <allen.baum@...>
Cc: Oscar Jupp <jupposcar@...>; tech-privileged@...
Subject: [EXT] Re: [RISC-V] [tech-privileged] Question about supervisor interrupt in M mode
Caution: EXT Email
I agree this part of the spec is hard to understand, and requires piecing together several diverse sources within the privileged spec.
I don’t think your clarifications below are quite correct. More inline:
How could that be true if privmode=M? You should never be able to trap to S-mode when executing in M-mode.
Not equivalent, since sip and sie are both masked by mideleg. That’s why the spec doesn’t need to explicitly mention mideleg here.
This is correct but that last term is unnecessary because of the masking of sip/sie.
That’s putting it mildly!