Re: Question about mideleg

Jeff Scott



I don’t agree that a machine mode interrupt (MEI, MSI, MTI) delegated to supervisor mode shows up in SIP as the supervisor version (SEI, SSI, STI) and not the machine version (MEI, MSI, MTI).


From the spec “The sip and sie registers are subsets of the mip and mie registers. Reading any implemented

field, or writing any writable field, of sip/sie effects a read or write of the homonymous field

of mip/mie.”


This discussion has come up before by the way.  If we updated the spec as a result of the last discussion, this wouldn’t have come up again.




From: tech-privileged@... <tech-privileged@...> On Behalf Of Allen Baum via
Sent: Wednesday, December 7, 2022 3:52 PM
To: Scott Johnson <scott.johnson@...>
Cc: Oscar Jupp <jupposcar@...>; tech-privileged@...; tech-privileged@...
Subject: [EXT] Re: [RISC-V] [tech-privileged] Question about mideleg


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I was looking figure 4.6 of the priv spec, and it does show STIP as bit 5, not bit 7. Bit 7 is MTIP, and it is invisible to Smode.

That's why the interrupt pending bit shows up in bit 5 if delegated, but bit 7 if not.


MTIP is NOT driven by the PLIC; the PLIC only sends external interrupts, not timer interrupts (which correspond to bits xstatus[11..9]


The timer interrupt can only be reset by writing the MTIMECMP CSR, which is M-only. An implementation could have a custom alias to that that would enable Smode to write it,

but that;s dangerous, as that means that Scode could prevent Mmode from getting timer interrupts by setting the CSR to a value in the far future.


On Wed, Dec 7, 2022 at 9:59 AM Scott Johnson <scott.johnson@...> wrote:

Comments embedded:

On Dec 7, 2022, at 11:39 AM, Allen Baum via <> wrote:


As far as I can tell,  an implementation may, but is not required to,  disallow it. 


I suspect all implementations disallow it, by forcing those bits in mideleg to 0. OpenSBI does not attempt to delegate those interrupts.[1]

If it is delegated, it shows up in the SIP. STIP bit


How so? I would expect it to show up in SIP[7], which is defined as 0 in the privileged spec, but corresponds to the MTIP bit. There is no mechanism for an interrupt to show up in a different position in SIP vs MIP.


But, if it is delegated, then it can only be cleared by an ECALL to Mmode SW..


MTIP is controlled by a wire driven by a memory-mapped interrupt controller (e.g. PLIC). If an SBI decided to delegate MTI to S-mode then they might also allow S-mode software to access the interrupt controller too, removing any need for an ECALL.



[1] but line 200 apparently has a typo and should say “S-mode interrupts” instead of “M-mode interrupts"

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