1. Messages
  2. Question about mideleg

Re: Question about mideleg

Scott Johnson
 


On Dec 7, 2022, at 7:35 PM, Allen Baum <allen.baum@...> wrote:

Hmm, I misread that, and re-reading: this implies that sip.MTIP is not necessarily 0. 
I thought it had to be zero because everything Mmode related is normally hidden from S-mode for virtualization reasons.
This puzzles me

You seem to be confused by the names of the two interrupts MTI and STI. Think of them not as Machine/Supervisor but as Timer Interrupts A and B.

One of the two is traditionally delegated to S-mode via mideleg. But not necessarily.

If mideleg[5] is 0 then STIP is M-mode and hidden from S-mode. If mideleg[5] is 1 then STIP is S-mode and visible to both M-mode and S-mode.

If mideleg[7] is 0 then MTIP is M-mode and hidden from S-mode. If mideleg[7] is 1 then MTIP is S-mode and visible to both M-mode and S-mode.



It also puzzles me that an interrupt could set two different bits in xIP in hardware.

That doesn’t happen.
Join {tech-privileged@lists.riscv.org to automatically receive all group messages.