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Re: Question about mideleg

Jeff Scott
 

Agree Scott.  There really is no sip register.  sip is mip & mideleg.

 

Jeff

 

From: tech-privileged@... <tech-privileged@...> On Behalf Of Scott Johnson via lists.riscv.org
Sent: Wednesday, December 7, 2022 7:51 PM
To: Allen Baum <allen.baum@...>
Cc: tech-privileged@...
Subject: [EXT] Re: [RISC-V] [tech-privileged] Question about mideleg

 

Caution: EXT Email

 

On Dec 7, 2022, at 7:35 PM, Allen Baum <allen.baum@...> wrote:

 

Hmm, I misread that, and re-reading: this implies that sip.MTIP is not necessarily 0. 

I thought it had to be zero because everything Mmode related is normally hidden from S-mode for virtualization reasons.

This puzzles me

 

You seem to be confused by the names of the two interrupts MTI and STI. Think of them not as Machine/Supervisor but as Timer Interrupts A and B.

 

One of the two is traditionally delegated to S-mode via mideleg. But not necessarily.

 

If mideleg[5] is 0 then STIP is M-mode and hidden from S-mode. If mideleg[5] is 1 then STIP is S-mode and visible to both M-mode and S-mode.

 

If mideleg[7] is 0 then MTIP is M-mode and hidden from S-mode. If mideleg[7] is 1 then MTIP is S-mode and visible to both M-mode and S-mode.

 

 



It also puzzles me that an interrupt could set two different bits in xIP in hardware.

 

That doesn’t happen.

 

 
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