Re: Non-idempotent PMA and table walk accesses
David Kruckemyer
To clarify, in my previous email, I was taking a rather narrow view of the idempotent/non-idempotent attribute as applied to a memory location. One could broaden that definition to include system state, so that even if the underlying memory location was idempotent in the "reads return the last value written" sense, system side-effects would make the location non-idempotent. But that doesn't neatly apply to performance counters (and possibly other state). This just seems to highlight is that architectural specification is hard. Returning to my initial query, I'm still trying to understand what table walks to non-idempotent locations mean generally. If we assume the colloquial meaning of non-idempotent is "don't speculate" (ignoring the side-effects of the location or on other state), it would seem that a table walk access to a non-idempotent location could not be performed until all previous instructions were guaranteed not to trap. Is that the intent? Regardless, I'll put in another plug for commentary stating that the architecture strongly recommends that memory management data structures be located in idempotent regions. Cheers, David On Mon, May 18, 2020 at 6:56 PM Greg Favor <gfavor@...> wrote:
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